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UPD44164184F5-E40-EQ1 PDF预览

UPD44164184F5-E40-EQ1

更新时间: 2024-11-19 22:15:59
品牌 Logo 应用领域
日电电子 - NEC 存储内存集成电路静态存储器双倍数据速率
页数 文件大小 规格书
32页 391K
描述
18M-BIT DDRII SRAM 4-WORD BURST OPERATION

UPD44164184F5-E40-EQ1 技术参数

是否Rohs认证:不符合生命周期:Transferred
包装说明:13 X 15 MM, PLASTIC, BGA-165Reach Compliance Code:compliant
风险等级:5.84Is Samacsys:N
最长访问时间:0.45 ns其他特性:PIPELINED ARCHITECTURE
JESD-30 代码:R-PBGA-B165JESD-609代码:e0
长度:15 mm内存密度:18874368 bit
内存集成电路类型:DDR SRAM内存宽度:18
功能数量:1端子数量:165
字数:1048576 words字数代码:1000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:1MX18
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.51 mm
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:13 mm
Base Number Matches:1

UPD44164184F5-E40-EQ1 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD44164084, 44164184, 44164364  
18M-BIT DDRII SRAM  
4-WORD BURST OPERATION  
Description  
The µPD44164084 is a 2,097,152-word by 8-bit, the µPD44164184 is a 1,048,576-word by 18-bit and the  
µPD44164364 is a 524,288-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS  
technology using full CMOS six-transistor memory cell.  
The µPD44164084, µPD44164184 and µPD44164364 integrates unique synchronous peripheral circuitry and a  
burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and  
/K.  
These products are suitable for application which require synchronous operation, high speed, low voltage, high  
density and wide bit configuration.  
These products are packaged in 165-pin PLASTIC BGA.  
Features  
1.8 ± 0.1 V power supply and HSTL I/O  
DLL circuitry for wide output data valid window and future frequency scaling  
Pipelined double data rate operation  
Common data input/output bus  
Four-tick burst for reduced address frequency  
Two input clocks (K and /K) for precise DDR timing at clock rising edges only  
Two output clocks (C and /C) for precise flight time  
and clock skew matching-clock and data delivered together to receiving device  
Internally self-timed write control  
Clock-stop capability with µs restart  
User programmable impedance output  
Fast clock cycle time : 4.0 ns (250 MHz), 5.0 ns (200 MHz), 6.0 ns (167 MHz)  
Simple control logic for easy depth expansion  
JTAG boundary scan  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. M15822EJ7V1DS00 (7th edition)  
Date Published July 2004 NS CP(K)  
Printed in Japan  
The mark  
shows major revised points.  
2001  

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