Datasheet > UPD44164185BF5-E35-EQ3

UPD44164185BF5-E35-EQ3

更新时间： 2024-11-25 04:38:31

品牌	Logo	应用领域
瑞萨 - RENESAS		双倍数据速率静态存储器
页数	文件大小	规格书
35页	461K
描述
1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, PLASTIC, BGA-165

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

UPD44164185BF5-E35-EQ3 数据手册

浏览型号UPD44164185BF5-E35-EQ3的Datasheet PDF文件第2页

浏览型号UPD44164185BF5-E35-EQ3的Datasheet PDF文件第3页

浏览型号UPD44164185BF5-E35-EQ3的Datasheet PDF文件第4页

浏览型号UPD44164185BF5-E35-EQ3的Datasheet PDF文件第5页

浏览型号UPD44164185BF5-E35-EQ3的Datasheet PDF文件第6页

Datasheet

μPD44164095B

μPD44164185B

R10DS0016EJ0200

Rev.2.00

18M-BIT DDR II SRAM SEPARATE I/O

2-WORD BURST OPERATION

October 6, 2011

Description

The μPD44164095B is a 2,097,152-word by 9-bit and the μPD44164185B is a 1,048,576-word by 18-bit

synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-

transistor memory cell.

The μPD44164095B and μPD44164185B integrate unique synchronous peripheral circuitry and a burst

counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K

and K#. These products are suitable for application which require synchronous operation, high speed, low

voltage, high density and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

Features

• 1.8 0.1 V power supply

• 165-pin PLASTIC BGA (13 x 15)

• HSTL interface

• PLL circuitry for wide output data valid window and future frequency scaling

• Separate independent read and write data ports

• DDR read or write operation initiated each cycle

• Pipelined double data rate operation

• Separate data input/output bus

• Two-tick burst for low DDR transaction size

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two output clocks (C and C#) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.

• User programmable impedance output (35 to 70 Ω)

• Fast clock cycle time : 3.3 ns (300 MHz), 3.5 ns (287 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)

• Simple control logic for easy depth expansion

• JTAG 1149.1 compatible test access port

R10DS0016EJ0200 Rev.2.00

October 6, 2011

Page 1 of 34

12 3 4 5 6 7...35

中文翻译

下载PDF

与UPD44164185BF5-E35-EQ3相关器件

型号	品牌	获取价格	描述	数据表
UPD44164185BF5-E35Y-EQ3	RENESAS	获取价格	1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, PLASTIC, BGA-165
UPD44164185BF5-E35Y-EQ3-A	RENESAS	获取价格	1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
UPD44164185BF5-E40Y-EQ3	RENESAS	获取价格	1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, PLASTIC, BGA-165
UPD44164185BF5-E40Y-EQ3-A	RENESAS	获取价格	1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
UPD44164185BF5-E50-EQ3	RENESAS	获取价格	1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, PLASTIC, BGA-165
UPD44164185F5-E40-EQ1	NEC	获取价格	18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION
UPD44164185F5-E50-EQ1	NEC	获取价格	18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION
UPD44164185F5-E60-EQ1	NEC	获取价格	18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION
UPD44164362AF5-E33-EQ2	NEC	获取价格	DDR SRAM, 512KX36, CMOS, PBGA165, 13 X 5 MM, PLASTIC, BGA-165
UPD44164362AF5-E33-EQ2-A	NEC	获取价格	DDR SRAM, 512KX36, CMOS, PBGA165, 13 X 5 MM, LEAD FREE, PLASTIC, BGA-165

与UPD44164185BF5-E35-EQ3相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

38
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

30
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

58
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

54

产品中心

服务支持

精选活动

关于我们

帮助中心

UPD44164185BF5-E35-EQ3

UPD44164185BF5-E35-EQ3 数据手册

与UPD44164185BF5-E35-EQ3相关器件

与UPD44164185BF5-E35-EQ3相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

UPD44164185BF5-E35-EQ3

UPD44164185BF5-E35-EQ3 数据手册

与UPD44164185BF5-E35-EQ3相关器件

与UPD44164185BF5-E35-EQ3相关文章

您还可以找

您在本页遇到什么问题？