Datasheet > UPD44164362AF5-E40-EQ2

UPD44164362AF5-E40-EQ2

更新时间： 2024-11-21 06:59:19

品牌	Logo	应用领域
日电电子 - NEC		双倍数据速率静态存储器
页数	文件大小	规格书
40页	374K
描述
DDR SRAM, 512KX36, CMOS, PBGA165, 13 X 5 MM, PLASTIC, BGA-165

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DATA SHEET

MOS INTEGRATED CIRCUIT

μPD44164082A, 44164092A, 44164182A, 44164362A

18M-BIT DDRII SRAM

2-WORD BURST OPERATION

Description

The μPD44164082A is a 2,097,152-word by 8-bit, the μPD44164092A is a 2,097,152-word by 9-bit, the μPD44164182A

is a 1,048,576-word by 18-bit and the μPD44164362A is a 524,288-word by 36-bit synchronous double data rate static

RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The μPD44164082A, μPD44164092A, μPD44164182A and μPD44164362A integrate unique synchronous peripheral

circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive

edge of K and K#.

These products are suitable for application which require synchronous operation, high speed, low voltage, high

density and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

Features

• 1.8 ± 0.1 V power supply

• 165-pin PLASTIC BGA package (13 x 15)

• HSTL interface

• PLL circuitry for wide output data valid window and future frequency scaling

• Pipelined double data rate operation

• Common data input/output bus

• Two-tick burst for low DDR transaction size

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two output clocks (C and C#) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.

• User programmable impedance output

<R>

• Fast clock cycle time : 3.3 ns (300 MHz), 3.7 ns (270 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)

• Simple control logic for easy depth expansion

• JTAG boundary scan

• Operating ambient temperature: Commercial T^A= 0 to +70°C

(-E33, -E37, -E40, -E50)

Industrial T^A= –40 to +85°C (-E37Y, -E40Y, -E50Y)

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M17767EJ3V0DS00 (3rd edition)

Date Published February 2007 NS CP(N)

Printed in Japan

2006

The mark <R> shows major revised points.

The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.

12 3 4 5 6 7...40

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与UPD44164362AF5-E40-EQ2相关器件

型号	品牌	获取价格	描述	数据表
UPD44164362AF5-E40-EQ2-A	NEC	获取价格	DDR SRAM, 512KX36, CMOS, PBGA165, 13 X 5 MM, LEAD FREE, PLASTIC, BGA-165
UPD44164362AF5-E50-EQ2-A	RENESAS	获取价格	512KX36 DDR SRAM, PBGA165, 13 X 5 MM, LEAD FREE, PLASTIC, BGA-165
UPD44164362F5-E30-EQ1	RENESAS	获取价格	DDR SRAM, 512KX36, 0.27ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165
UPD44164362F5-E33-EQ1	RENESAS	获取价格	DDR SRAM, 512KX36, 0.29ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165
UPD44164362F5-E50-EQ1	NEC	获取价格	18M-BIT DDRII SRAM 2-WORD BURST OPERATION
UPD44164362F5-E60-EQ1	NEC	获取价格	18M-BIT DDRII SRAM 2-WORD BURST OPERATION
UPD44164364AF5-E33-EQ2	NEC	获取价格	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, BGA-165
UPD44164364AF5-E33-EQ2-A	NEC	获取价格	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
UPD44164364AF5-E40-EQ2	NEC	获取价格	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, BGA-165
UPD44164364AF5-E40-EQ2-A	NEC	获取价格	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165

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