Datasheet > UPD44164365AF5-E50-EQ2

UPD44164365AF5-E50-EQ2

更新时间： 2024-02-24 22:38:18

品牌	Logo	应用领域
日电电子 - NEC		时钟双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
40页	382K
描述
IC,SYNC SRAM,DDR,512KX36,CMOS,BGA,165PIN,PLASTIC

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

UPD44164365AF5-E50-EQ2 数据手册

浏览型号UPD44164365AF5-E50-EQ2的Datasheet PDF文件第2页

浏览型号UPD44164365AF5-E50-EQ2的Datasheet PDF文件第3页

浏览型号UPD44164365AF5-E50-EQ2的Datasheet PDF文件第4页

浏览型号UPD44164365AF5-E50-EQ2的Datasheet PDF文件第5页

浏览型号UPD44164365AF5-E50-EQ2的Datasheet PDF文件第6页

DATA SHEET

MOS INTEGRATED CIRCUIT

PD44164085A, 44164095A, 44164185A, 44164365A

18M-BIT DDRII SRAM SEPARATE I/O

2-WORD BURST OPERATION

Description

The μPD44164085A is a 2,097,152-word by 8-bit, the μPD44164095A is a 2,097,152-word by 9-bit, the μPD44164185A

is a 1,048,576-word by 18-bit and the μPD44164365A is a 524,288-word by 36-bit synchronous double data rate static

RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The μPD44164085A, μPD44164095A, μPD44164185A and μPD44164365A integrate unique synchronous peripheral

circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive

edge of K and K#.

These products are suitable for application which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

Features

• 1.8 ± 0.1 V power supply

• 165-pin PLASTIC BGA package (13 x 15)

• HSTL interface

• PLL circuitry for wide output data valid window and future frequency scaling

• Separate independent read and write data ports

• DDR read or write operation initiated each cycle

• Pipelined double data rate operation

• Separate data input/output bus

• Two-tick burst for low DDR transaction size

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two output clocks (C and C#) for precise flight time and clock skew matching-clock

and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.

• User programmable impedance output

<R>

• Fast clock cycle time : 3.3 ns (300 MHz), 3.7 ns (270 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)

• Simple control logic for easy depth expansion

• JTAG boundary scan

• Operating ambient temperature: Commercial T^A= 0 to +70°C

(-E33, -E37, -E40, -E50)

Industrial T^A= –40 to +85°C (-E37Y, -E40Y, -E50Y)

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M17769EJ3V0DS00 (3rd edition)

Date Published February 2007 NS CP(N)

Printed in Japan

2006

The mark <R> shows major revised points.

The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.

12 3 4 5 6 7...40

下载PDF

与UPD44164365AF5-E50-EQ2相关器件

型号	品牌	描述	获取价格	数据表
UPD44164365AF5-E50-EQ2-A	RENESAS	512KX36 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165	获取价格
UPD44164365F5-E50-EQ1	NEC	18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION	获取价格
UPD44164365F5-E60-EQ1	NEC	18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION	获取价格
UPD44165082	NEC	18M-BIT QDRII SRAM 2-WORD BURST OPERATION	获取价格
UPD44165082AF5-E40-EQ2	NEC	2MX8 QDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, PLASTIC, BGA-165	获取价格
UPD44165082AF5-E40-EQ2-A	RENESAS	2MX8 QDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

UPD44164365AF5-E50-EQ2

UPD44164365AF5-E50-EQ2 数据手册

与UPD44164365AF5-E50-EQ2相关器件

与UPD44164365AF5-E50-EQ2相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

UPD44164365AF5-E50-EQ2

UPD44164365AF5-E50-EQ2 数据手册

与UPD44164365AF5-E50-EQ2相关器件

与UPD44164365AF5-E50-EQ2相关文章

您还可以找

您在本页遇到什么问题？