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UPD44164185AF5-E33-EQ2 PDF预览

UPD44164185AF5-E33-EQ2

更新时间: 2024-11-20 19:29:27
品牌 Logo 应用领域
日电电子 - NEC 双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
40页 382K
描述
DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, BGA-165

UPD44164185AF5-E33-EQ2 技术参数

是否Rohs认证:不符合生命周期:Transferred
包装说明:13 X 15 MM, PLASTIC, BGA-165Reach Compliance Code:compliant
风险等级:5.84Is Samacsys:N
最长访问时间:0.45 ns其他特性:PIPELINED ARCHITECTURE
JESD-30 代码:R-PBGA-B165JESD-609代码:e0
长度:15 mm内存密度:18874368 bit
内存集成电路类型:DDR SRAM内存宽度:18
功能数量:1端子数量:165
字数:1048576 words字数代码:1000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:1MX18
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.51 mm
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:13 mm
Base Number Matches:1

UPD44164185AF5-E33-EQ2 数据手册

 浏览型号UPD44164185AF5-E33-EQ2的Datasheet PDF文件第2页浏览型号UPD44164185AF5-E33-EQ2的Datasheet PDF文件第3页浏览型号UPD44164185AF5-E33-EQ2的Datasheet PDF文件第4页浏览型号UPD44164185AF5-E33-EQ2的Datasheet PDF文件第5页浏览型号UPD44164185AF5-E33-EQ2的Datasheet PDF文件第6页浏览型号UPD44164185AF5-E33-EQ2的Datasheet PDF文件第7页 
DATA SHEET  
MOS INTEGRATED CIRCUIT  
PD44164085A, 44164095A, 44164185A, 44164365A  
μ
18M-BIT DDRII SRAM SEPARATE I/O  
2-WORD BURST OPERATION  
Description  
The μPD44164085A is a 2,097,152-word by 8-bit, the μPD44164095A is a 2,097,152-word by 9-bit, the μPD44164185A  
is a 1,048,576-word by 18-bit and the μPD44164365A is a 524,288-word by 36-bit synchronous double data rate static  
RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.  
The μPD44164085A, μPD44164095A, μPD44164185A and μPD44164365A integrate unique synchronous peripheral  
circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive  
edge of K and K#.  
These products are suitable for application which require synchronous operation, high speed, low voltage, high density  
and wide bit configuration.  
These products are packaged in 165-pin PLASTIC BGA.  
Features  
1.8 ± 0.1 V power supply  
165-pin PLASTIC BGA package (13 x 15)  
HSTL interface  
PLL circuitry for wide output data valid window and future frequency scaling  
Separate independent read and write data ports  
DDR read or write operation initiated each cycle  
Pipelined double data rate operation  
Separate data input/output bus  
Two-tick burst for low DDR transaction size  
Two input clocks (K and K#) for precise DDR timing at clock rising edges only  
Two output clocks (C and C#) for precise flight time and clock skew matching-clock  
and data delivered together to receiving device  
Internally self-timed write control  
Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.  
User programmable impedance output  
<R>  
<R>  
Fast clock cycle time : 3.3 ns (300 MHz), 3.7 ns (270 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)  
Simple control logic for easy depth expansion  
JTAG boundary scan  
Operating ambient temperature: Commercial TA = 0 to +70°C  
(-E33, -E37, -E40, -E50)  
Industrial TA = –40 to +85°C (-E37Y, -E40Y, -E50Y)  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. M17769EJ3V0DS00 (3rd edition)  
Date Published February 2007 NS CP(N)  
Printed in Japan  
2006  
The mark <R> shows major revised points.  
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.  

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DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, BGA-165
UPD44164185AF5-E40Y-EQ2-A RENESAS

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