UL634H256
Low Voltage PowerStore 32K x 8 nvSRAM
Features
Description
F High-performance CMOS non-
The UL634H256 has two separate high performance and ease of use
volatile static RAM 32768 x 8 bits modes of operation: SRAM mode of a fast SRAM with nonvolatile
F 45 and 55 ns Access Times
F 20 and 25 ns Output Enable
Access Times
F ICC = 8 mA at 200 ns Cycle Time
F Automatic STORE to EEPROM
on Power Down using external
capacitor
and nonvolatile mode. In SRAM data integrity.
mode, the memory operates as an STORE cycles also may be initia-
ordinary static RAM. In nonvolatile ted under user control via a soft-
operation, data is transferred in ware sequence or via a single pin
parallel from SRAM to EEPROM or (HSB).
from EEPROM to SRAM. In this Once a STORE cycle is initiated,
mode SRAM functions are disab- further input or output are disabled
F Software initiated STORE
F Automatic STORE Timing
F 105 STORE cycles to EEPROM
F 10 years data retention in
EEPROM
led.
until the cycle is completed.
The UL634H256 is a fast static Because a sequence of addresses
RAM (45 and 55 ns), with a nonvo- is used for STORE initiation, it is
latile electrically erasable PROM important that no other read or
(EEPROM) element incorporated write accesses intervene in the
F Automatic RECALL on Power Up in each static memory cell. The sequence or the sequence will be
F Software RECALL Initiation
F Unlimited RECALL cycles from
EEPROM
SRAM can be read and written an aborted.
unlimited number of times, while RECALL cycles may also be initia-
independent nonvolatile data resi- ted by a software sequence.
F Wide voltage range: 2.7 ... 3.6 V
F Operating temperature ranges:
0 to 70 °C
des in EEPROM.
Internally, RECALL is a two step
Data transfers from the SRAM to procedure. First, the SRAM data is
the EEPROM (the STORE opera- cleared and second, the nonvola-
tion) take place automatically upon tile information is transferred into
power down using charge stored in the SRAM cells.
an external 100 mF capacitor. The RECALL operation in no way
Transfers from the EEPROM to the alters the data in the EEPROM
SRAM (the RECALL operation) cells. The nonvolatile data can be
take place automatically on power recalled an unlimited number of
-40 to 85 °C
F CECC 90000 Quality Standard
F ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
F Packages: SOP32 (300 mil)
TSOP32 (Type I)
up.
times.
The UL634H256 combines the
Pin Description
Pin Configuration
Signal Name Signal Description
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32
31
30
VCAP
A14
A12
A7
VCCX
HSB
W
1
n.c.
A10
E
G
A11
A9
2
2
A0 - A14
Address Inputs
Data In/Out
3
3
4
DQ0 - DQ7
29 DQ7
A13
A8
4
A8
5
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A6
5
28
27
26
25
24
23
22
21
20
19
18
17
A13
W
Chip Enable
6
A5
A9
A11
G
6
E
7
A4
HSB
VCCX
VCAP
A14
A12
A7
7
Output Enable
Write Enable
8
A3
8
G
SOP
TSOP
9
n.c.
A2
n.c.
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
9
10
11
12
13
14
15
16
10
11
12
13
14
15
16
W
A1
A0
VCCX
VSS
VCAP
Power Supply Voltage
Ground
A6
DQ0
DQ1
DQ2
VSS
A1
A5
A2
A4
Capacitor
n.c.
A3
Top View
Top View
Hardware Controlled Store/Busy
HSB
1
January 09, 2002