UL634H256
Low Voltage PowerStore 32K x 8 nvSRAM
Features
Description
The UL634H256 has two separate The UL634H256 combines the
! High-performance CMOS non-
volatile static RAM 32768 x 8 bits modes of operation: SRAM mode high performance and ease of use
! 35 and 45 ns Access Times
! 15 and 20 ns Output Enable
Access Times
and nonvolatile mode. In SRAM of a fast SRAM with nonvolatile
mode, the memory operates as an data integrity.
ordinary static RAM. In nonvolatile STORE cycles also may be initia-
operation, data is transferred in ted under user control via a soft-
parallel from SRAM to EEPROM or ware sequence or via a single pin
from EEPROM to SRAM. In this (HSB).
! ICC = 8 mA at 200 ns Cycle Time
! Automatic STORE to EEPROM
on Power Down using external
capacitor
mode SRAM functions are disab- Once a STORE cycle is initiated,
! Software initiated STORE
! Automatic STORE Timing
! 105 STORE cycles to EEPROM
! 10 years data retention in
EEPROM
led.
further input or output are disabled
The UL634H256 is a fast static until the cycle is completed.
RAM (35 and 45 ns), with a nonvo- Because a sequence of addresses
latile electrically erasable PROM is used for STORE initiation, it is
(EEPROM) element incorporated important that no other read or
! Automatic RECALL on Power Up in each static memory cell. The write accesses intervene in the
! Software RECALL Initiation
! Unlimited RECALL cycles from
EEPROM
SRAM can be read and written an sequence or the sequence will be
unlimited number of times, while aborted.
independent nonvolatile data resi- RECALL cycles may also be initia-
! Wide voltage range: 2.7 ... 3.6 V
(3.0 ... 3.6 V for 35 ns type)
! Operating temperature range:
0 to 70 °C
des in EEPROM.
ted by a software sequence.
Data transfers from the SRAM to Internally, RECALL is a two step
the EEPROM (the STORE opera- procedure. First, the SRAM data is
tion) take place automatically upon cleared and second, the nonvola-
power down using charge stored in tile information is transferred into
an external 68 µF capacitor. Trans- the SRAM cells.
-40 to 85 °C (only 45 ns)
-40 to 125 °C (only 45 ns)
! QS 9000 Quality Standard
! ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
! Packages: SOP32 (300 mil)
TSOP32 (Type I)
fers from the EEPROM to the The RECALL operation in no way
SRAM (the RECALL operation) alters the data in the EEPROM
take place automatically on power cells. The nonvolatile data can be
up.
recalled an unlimited number of
times.
Pin Description
Pin Configuration
Signal Name Signal Description
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32
31
30
VCAP
A14
A12
A7
VCCX
HSB
W
1
n.c.
A10
E
G
A11
A9
2
2
A0 - A14
DQ0 - DQ7
Address Inputs
Data In/Out
3
3
4
29 DQ7
A13
A8
4
A8
5
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A6
5
28
27
26
25
24
23
22
21
20
19
18
17
A13
W
Chip Enable
6
A5
A9
6
E
7
A4
A11
G
HSB
VCCX
VCAP
A14
A12
A7
7
Output Enable
Write Enable
8
A3
8
G
W
SOP
TSOP
9
n.c.
A2
n.c.
A10
E
9
10
11
12
13
14
15
16
10
11
12
13
14
15
16
A1
VCCX
VSS
VCAP
Power Supply Voltage
Ground
Capacitor
A0
DQ7
DQ6
DQ5
DQ4
DQ3
A6
DQ0
DQ1
DQ2
VSS
A1
A5
A2
A4
n.c.
A3
Top View
Top View
Hardware Controlled Store/Busy
HSB
1
October 20, 2003
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