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UL634H256SK55G1 PDF预览

UL634H256SK55G1

更新时间： 2024-09-21 04:05:11
品牌 Logo 应用领域
SIMTEK 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
14页 158K
描述
Non-Volatile SRAM, 32KX8, 55ns, CMOS, PDSO32, 0.300 INCH, SOP-32

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UL634H256SK55G1 数据手册

 浏览型号UL634H256SK55G1的Datasheet PDF文件第2页浏览型号UL634H256SK55G1的Datasheet PDF文件第3页浏览型号UL634H256SK55G1的Datasheet PDF文件第4页浏览型号UL634H256SK55G1的Datasheet PDF文件第5页浏览型号UL634H256SK55G1的Datasheet PDF文件第6页浏览型号UL634H256SK55G1的Datasheet PDF文件第7页 
UL634H256  
Low Voltage PowerStore 32K x 8 nvSRAM  
Features  
Description  
F High-performance CMOS non-  
The UL634H256 has two separate The UL634H256 combines the  
volatile static RAM 32768 x 8 bits modes of operation: SRAM mode high performance and ease of use  
F 35, 45 and 55 ns Access Times  
F 15, 20 and 25 ns Output Enable  
Access Times  
F ICC = 8 mA at 200 ns Cycle Time  
F Automatic STORE to EEPROM  
on Power Down using external  
capacitor  
and nonvolatile mode. In SRAM of a fast SRAM with nonvolatile  
mode, the memory operates as an data integrity.  
ordinary static RAM. In nonvolatile STORE cycles also may be initia-  
operation, data is transferred in ted under user control via a soft-  
parallel from SRAM to EEPROM or ware sequence or via a single pin  
from EEPROM to SRAM. In this (HSB).  
mode SRAM functions are disab- Once a STORE cycle is initiated,  
F Software initiated STORE  
F Automatic STORE Timing  
F 105 STORE cycles to EEPROM  
F 10 years data retention in  
EEPROM  
led.  
further input or output are disabled  
The UL634H256 is a fast static until the cycle is completed.  
RAM (35, 45 and 55 ns), with a Because a sequence of addresses  
nonvolatile electrically erasable is used for STORE initiation, it is  
PROM (EEPROM) element incor- important that no other read or  
F Automatic RECALL on Power Up porated in each static memory cell. write accesses intervene in the  
F Software RECALL Initiation  
F Unlimited RECALL cycles from  
EEPROM  
The SRAM can be read and written sequence or the sequence will be  
an unlimited number of times, while aborted.  
independent nonvolatile data resi- RECALL cycles may also be initia-  
F Wide voltage range: 2.7 ... 3.6 V  
(3.0 ... 3.6 V for 35 ns type)  
F Operating temperature range:  
0 to 70 °C  
des in EEPROM.  
ted by a software sequence.  
Data transfers from the SRAM to Internally, RECALL is a two step  
the EEPROM (the STORE opera- procedure. First, the SRAM data is  
tion) take place automatically upon cleared and second, the nonvola-  
-40 to 85 °C (only 45 and 55 ns) power down using charge stored in tile information is transferred into  
F CECC 90000 Quality Standard  
F ESD protection > 2000 V  
(MIL STD 883C M3015.7-HBM)  
F Packages: SOP32 (300 mil)  
TSOP32 (Type I)  
an external 68 µF capacitor. Trans- the SRAM cells.  
fers from the EEPROM to the The RECALL operation in no way  
SRAM (the RECALL operation) alters the data in the EEPROM  
take place automatically on power cells. The nonvolatile data can be  
up.  
recalled an unlimited number of  
times.  
Pin Description  
Pin Configuration  
Signal Name Signal Description  
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
32  
31  
30  
VCAP  
A14  
A12  
A7  
VCCX  
HSB  
W
1
n.c.  
A10  
E
G
A11  
A9  
2
2
A0 - A14  
Address Inputs  
Data In/Out  
3
3
4
DQ0 - DQ7  
29 DQ7  
A13  
A8  
4
A8  
5
DQ6  
DQ5  
DQ4  
DQ3  
VSS  
DQ2  
DQ1  
DQ0  
A0  
A6  
5
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A13  
W
Chip Enable  
6
A5  
A9  
A11  
G
6
E
7
A4  
HSB  
VCCX  
VCAP  
A14  
A12  
A7  
7
Output Enable  
Write Enable  
8
A3  
8
G
SOP  
TSOP  
9
n.c.  
A2  
n.c.  
A10  
E
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
9
10  
11  
12  
13  
14  
15  
16  
10  
11  
12  
13  
14  
15  
16  
W
A1  
A0  
VCCX  
VSS  
VCAP  
Power Supply Voltage  
Ground  
A6  
DQ0  
DQ1  
DQ2  
VSS  
A1  
A5  
A2  
A4  
Capacitor  
n.c.  
A3  
Top View  
Top View  
Hardware Controlled Store/Busy  
HSB  
1
July 03, 2002  
1234567...14

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UL635H256BSK45 CYPRESS

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 		32KX8 NON-VOLATILE SRAM, 55ns, PDSO28, 0.330 INCH, SOP-28

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