Datasheet
Tsi206 Primary Side Monitor with Inrush
Control
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•
Industrial controllers
Features
Single board computers
•
•
•
•
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Input voltage measurement (24 V or 48 V)
10-bit analog-to-digital converter (ADC)
Input voltage measurement accuracy 0.5%
Control of inrush current
Fuse status monitoring, high and low side
Primary current sensing and measurement
Primary side undervoltage, overvoltage and
brownout detection
Electronic circuit breaker function
Enable control for intermediate bus power
converter
Isolated PI-Link interface to secondary side
controller transmits primary voltage, current,
fuse status and input status data
Description
The Tsi206 is designed to monitor parameters on
the high voltage primary side of an on-card power
system in a distributed power architecture.
In a typical 24 V or 48 V application, the Tsi206
measures input voltage and current and transmits
the digitized values through the PI-Link interface to
the secondary side controller (Tsi257). It also
controls an external MOSFET to limit card inrush
current at startup. Programmable input overvoltage
(OV) and undervoltage (UV) detection are provided.
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Input UV shutdown accuracy <1%
Self-powered from 24 V or 48 V nominal
The Tsi206 provides on-off control for an isolated
power converter that supplies the intermediate bus
voltage for the card. It monitors the status of up to
four input fuses, both high side and low side. Fuse
status information is transmitted to the secondary
side through the serial PI-Link interface.
Applications
•
Telecom and datacom cards
ATCA (Advanced Telecom Compute
Architecture) systems
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Figure 1 — Typical application circuit
+
+
0 V
(Battery
return)
EMI
filter
Intermediate
bus (IB) brick
C4
Enable
IB rail
-
Power connections
shown as
R5
R19
-
R3 R4
R1 R2
R17
Tsi206
VDD
OP1
ENABLE
TX_H
VDDO
Seat
(short pins)
R16
SHUNT
TX_L
BUSOFF
VCTRL
SEAT
CT
R21
Brick
shutdown
signal
from
Tsi257
OP2
C7
UV
FETA
SENSE_P
SENSE_OUT
SENSE_IN
SENSE_N
POR
Q2
C6
R13
VBATT
FUSE_H
R15
R22
C11
Monitor
signal
to
FUSE_L
R14
NC
R8
VBG
VSS
R6
Tsi257
R7
D1
R12
T1
Isolation
circuit
(see Fig. 7)
VSSO
AUX
BIAS
R9 R10
R20
C2
-48 V A
-48 V B
C3
Q1
Fuse A
Fuse B
Primary
Secondary
R11
C5
C1
R18
D2
MD533J
Note: High-side fuse monitoring is not shown – refer to Figure 8.
80C7000_MA001_01 April 2006
© Tundra Semiconductor Corporation
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