Datasheet > TP2635_13

TP2635_13

更新时间： 2024-09-21 01:14:51

品牌	Logo	应用领域
超科 - SUPERTEX		/
页数	文件大小	规格书
5页	624K
描述
P-Channel Enhancement-Mode Vertical DMOS FET

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中文翻译

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TP2635_13 数据手册

Supertex inc.

TP2635

P-Channel Enhancement-Mode

Vertical DMOS FET

Features

General Description

► Low threshold (-2.0V max.)

► High input impedance

► Low input capacitance

► Fast switching speeds

► Low on-resistance

This low threshold, enhancement-mode (normally-off)

transistor utilizes a vertical DMOS structure and Supertex’s

well-proven, silicon-gate manufacturing process. This

combination produces a device with the power handling

capabilities of bipolar transistors and the high input impedance

and positive temperature coefﬁcient inherent in MOS devices.

Characteristic of all MOS structures, this device is free

from thermal runaway and thermally-induced secondary

breakdown.

► Free from secondary breakdown

► Low input and output leakage

Applications

► Logic level interfaces - ideal for TTL and CMOS

Supertex’s vertical DMOS FETs are ideally suited to a wide

range of switching and amplifying applications where very

low threshold voltage, high breakdown voltage, high input

impedance, low input capacitance, and fast switching speeds

are desired.

► Solid state relays

► Battery operated systems

► Photo voltaic drives

► Analog switches

► General purpose line drivers

► Telecom switches

Ordering Information

Product Summary

R_DS(ON)

I_D(ON)

Part Number

Package Option

Packing

V_GS(th)

(max)

BV_DSS/BV_DGS

(max)

(min)

TP2635N3-G

3-Lead TO-92

1000/Bag

-350V

15Ω

-2.0A

-0.7V

TP2635N3-G P002

TP2635N3-G P003

Pin Conﬁguration

TP2635N3-G P005 3-Lead TO-92

TP2635N3-G P013

2000/Reel

DRAIN

TP2635N3-G P014

SOURCE

-G denotes a lead (Pb)-free / RoHS compliant package.

Contact factory for Wafer / Die availablity.

Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.

GATE

TO-92

Absolute Maximum Ratings

Parameter

Product Marking

Value

BV_DSS

BV_DGS

±20V

Drain-to-source voltage

Drain-to-gate voltage

SiTP

2 6 3 5

YYWW

YY = Year Sealed

WW = Week Sealed

= “Green” Packaging

Gate-to-source voltage

Operating and storage temperature

-55^OC to +150^OC

Package may or may not include the following marks: Si or

Absolute Maximum Ratings are those values beyond which damage to the device

may occur. Functional operation under these conditions is not implied. Continuous

operation of the device at the absolute rating level may affect device reliability. All

voltages are referenced to device ground.

TO-92

Typical Thermal Resistance

Package

θ_ja

TO-92

132^OC/W

Doc.# DSFP-TP2635

B081613

Supertex inc.

www.supertex.com

12 3 4 5

中文翻译

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与TP2635_13相关器件

型号	品牌	获取价格	描述	数据表
TP2635LG	ETC	获取价格	TRANSISTOR \| MOSFET \| P-CHANNEL \| 350V V(BR)DSS \| SO
TP2635N3	SUPERTEX	获取价格	P-Channel Enhancement-Mode Vertical DMOS FETs
TP2635N3-G	SUPERTEX	获取价格	P- Channel Enhancement-Mode Vertical DMOS FETs
TP2635N3-GP002	SUPERTEX	获取价格	Small Signal Field-Effect Transistor,
TP2635N3-GP003	SUPERTEX	获取价格	P-Channel Enhancement-Mode Vertical DMOS FET
TP2635N3-GP005	SUPERTEX	获取价格	Small Signal Field-Effect Transistor,
TP2635N3-GP013	SUPERTEX	获取价格	SMALL SIGNAL, FET
TP2635N3-GP014	SUPERTEX	获取价格	P-Channel Enhancement-Mode Vertical DMOS FET
TP2640	SUPERTEX	获取价格	P-Channel Enhancement-Mode Vertical DMOS FETs
TP2640	MICROCHIP	获取价格	This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS st

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