Datasheet > TP2640N3-GP003

TP2640N3-GP003

更新时间： 2024-11-29 15:54:55

品牌	Logo	应用领域
超科 - SUPERTEX		/
页数	文件大小	规格书
6页	710K
描述
SMALL SIGNAL, FET

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TP2640N3-GP003 数据手册

Supertex inc.

TP2640

P-Channel Enhancement-Mode

Vertical DMOS FET

Features

General Description

► Low threshold (-2.0V max.)

► High input impedance

► Low input capacitance

► Fast switching speeds

► Low on-resistance

This low threshold, enhancement-mode (normally-off)

transistor utilizes a vertical DMOS structure and Supertex’s

well-proven, silicon-gate manufacturing process. This

combination produces a device with the power handling

capabilities of bipolar transistors and the high input impedance

and positive temperature coefﬁcient inherent in MOS devices.

Characteristic of all MOS structures, this device is free

from thermal runaway and thermally-induced secondary

breakdown.

► Free from secondary breakdown

► Low input and output leakage

Applications

► Logic level interfaces - ideal for TTL and CMOS

Supertex’s vertical DMOS FETs are ideally suited to a wide

range of switching and amplifying applications where very

low threshold voltage, high breakdown voltage, high input

impedance, low input capacitance, and fast switching speeds

are desired.

► Solid state relays

► Battery operated systems

► Photo voltaic drives

► Analog switches

► General purpose line drivers

► Telecom switches

Ordering Information

Product Summary

Package

Option

R_DS(ON)

I_D(ON)

Part Number

Packing

V_GS(th)

BV_DSS/BV_DGS

(max)

(min)

TP2640LG-G

8-Lead SOIC

3-Lead TO-92

2500/Reel

1000/Bag

-400V

15Ω

-2.0A

-0.7V

TP2640N3-G

TP2640N3-G P002

TP2640N3-G P003

TP2640N3-G P005

TP2640N3-G P013

TP2640N3-G P014

Pin Conﬁguration

DRAIN

3-Lead TO-92

2000/Reel

DRAIN

GATE

SOURCE

N/C

-G denotes a lead (Pb)-free / RoHS compliant package.

Contact factory for Wafer / Die availablity.

Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.

SOURCE

GATE

Absolute Maximum Ratings

Parameter

8-Lead SOIC

TO-92

Value

Product Marking

Drain-to-source voltage

Drain-to-gate voltage

BV_DSS

BV_DGS

±20V

YY = Year Sealed

WW = Week Sealed

L = Lot Number

= “Green” Packaging

YYWW

Gate-to-source voltage

P2640

LLLL

Operating and storage temperature

-55^OC to +150^OC

Absolute Maximum Ratings are those values beyond which damage to the device

may occur. Functional operation under these conditions is not implied. Continuous

operation of the device at the absolute rating level may affect device reliability. All

voltages are referenced to device ground.

Package may or may not include the following marks: Si or

8-Lead SOIC

Typical Thermal Resistance

SiTP

2 6 4 0

YYWW

YY = Year Sealed

WW = Week Sealed

Package

8-Lead SOIC

TO-92

θ_ja

= “Green” Packaging

101^OC/W

132^OC/W

Package may or may not include the following marks: Si or

TO-92

Doc.# DSFP-TP2640

B081613

Supertex inc.

www.supertex.com

12 3 4 5 6

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与TP2640N3-GP003相关器件

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