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TP2640LG PDF预览

TP2640LG

更新时间： 2024-11-28 22:42:03
品牌 Logo 应用领域
超科 - SUPERTEX 晶体小信号场效应晶体管开关光电二极管输入元件
页数 文件大小 规格书
4页 459K
描述
P-Channel Enhancement-Mode Vertical DMOS FETs

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中文翻译

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TP2640LG 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SO-8
针数：8Reach Compliance Code：compliant
ECCN代码：EAR99风险等级：5.24
Is Samacsys：N其他特性：HIGH INPUT IMPEDANCE
配置：SINGLE WITH BUILT-IN DIODE最小漏源击穿电压：400 V
最大漏极电流 (ID)：0.21 A最大漏源导通电阻：15 Ω
FET 技术：METAL-OXIDE SEMICONDUCTOR最大反馈电容 (Crss)：12 pF
JEDEC-95代码：MS-012AAJESD-30 代码：R-PDSO-G8
JESD-609代码：e0元件数量：1
端子数量：8工作模式：ENHANCEMENT MODE
最高工作温度：150 °C封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED极性/信道类型：P-CHANNEL
功耗环境最大值：1.3 W最大功率耗散 (Abs)：1.3 W
认证状态：Not Qualified子类别：Other Transistors
表面贴装：YES端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED晶体管应用：SWITCHING
晶体管元件材料：SILICONBase Number Matches：1

TP2640LG 数据手册

 浏览型号TP2640LG的Datasheet PDF文件第2页浏览型号TP2640LG的Datasheet PDF文件第3页浏览型号TP2640LG的Datasheet PDF文件第4页 
TP2635  
TP2640  
Low Threshold  
P-Channel Enhancement-Mode  
Vertical DMOS FETs  
Ordering Information  
Order Number / Package  
BVDSS  
/
RDS(ON)  
(max)  
VGS(th)  
(max)  
ID(ON)  
(min)  
BVDGS  
-350V  
-400V  
SO-8  
–
TO-92  
Die†  
—
15Ω  
15Ω  
-2.0V  
-2.0V  
-0.7A  
-0.7A  
TP2635N3  
TP2640N3  
TP2640LG  
TP2640ND  
† MIL visual screening available.  
Features  
Low Threshold DMOS Technology  
These low threshold enhancement-mode (normally-off) transis-  
tors utilize a vertical DMOS structure and Supertex’s well-proven  
silicon-gate manufacturing process. This combination produces  
devices with the power handling capabilities of bipolar transistors  
and with the high input impedance and positive temperature  
coefficient inherent in MOS devices. Characteristic of all MOS  
structures, these devices are free from thermal runaway and  
thermally-induced secondary breakdown.  
❏
❏
❏
❏
❏
❏
❏
❏
Low threshold — -2.0V max.  
High input impedance  
Low input capacitance  
Fast switching speeds  
Low on resistance  
Free from secondary breakdown  
Low input and output leakage  
Supertex’s vertical DMOS FETs are ideally suited to a wide range  
of switching and amplifying applications where very low threshold  
voltage, highbreakdownvoltage, highinputimpedance, lowinput  
capacitance, and fast switching speeds are desired.  
Complementary N- and P-channel devices  
Applications  
Package Options  
❏
❏
❏
❏
❏
❏
❏
Logic level interfaces – ideal for TTL and CMOS  
Solid state relays  
Battery operated systems  
Photo voltaic drives  
Analog switches  
General purpose line drivers  
Telecom switches  
SGD  
TO-92  
1
2
3
4
8
7
6
5
NC  
NC  
S
D
D
D
D
Absolute Maximum Ratings  
Drain-to-Source Voltage  
BVDSS  
Drain-to-Gate Voltage  
BVDGS  
G
Gate-to-Source Voltage  
± 20V  
SO-8  
top view  
Operating and Storage Temperature  
Soldering Temperature*  
-55°C to +150°C  
300°C  
Note: See Package Outline section for dimensions.  
* Distance of 1.6 mm from case for 10 seconds.  
11/12/01  
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability  
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to  
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the  
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.  
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