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TP2104K1-G PDF预览

TP2104K1-G

更新时间: 2024-01-18 07:45:26
品牌 Logo 应用领域
美国微芯 - MICROCHIP 开关光电二极管晶体管
页数 文件大小 规格书
6页 702K
描述
160mA, 40V, P-CHANNEL, Si, SMALL SIGNAL, MOSFET, TO-236AB

TP2104K1-G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SOT-23
包装说明:SMALL OUTLINE, R-PDSO-G3针数:3
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8541.21.00.95风险等级:7.88
其他特性:LOW THRESHOLD配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:40 V最大漏极电流 (ID):0.16 A
最大漏源导通电阻:6 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss):10 pFJEDEC-95代码:TO-236AB
JESD-30 代码:R-PDSO-G3JESD-609代码:e3
湿度敏感等级:1元件数量:1
端子数量:3工作模式:ENHANCEMENT MODE
最高工作温度:150 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
极性/信道类型:P-CHANNEL认证状态:Not Qualified
表面贴装:YES端子面层:Matte Tin (Sn)
端子形式:GULL WING端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

TP2104K1-G 数据手册

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Supertex inc.  
TP2104  
P-Channel Enhancement-Mode  
Vertical DMOS FET  
Features  
General Description  
High input impedance and high gain  
Low power drive requirement  
Ease of paralleling  
This low threshold, enhancement-mode (normally-off) transistor  
utilizes a vertical DMOS structure and Supertex’s well-  
proven, silicon-gate manufacturing process. This combination  
produces a device with the power handling capabilities of  
bipolar transistors and the high input impedance and positive  
temperature coefficient inherent in MOS devices. Characteristic  
of all MOS structures, this device is free from thermal runaway  
and thermally-induced secondary breakdown.  
Low CISS and fast switching speeds  
Excellent thermal stability  
Integral source-drain diode  
Free from secondary breakdown  
Applications  
Supertex’s vertical DMOS FETs are ideally suited to a wide  
range of switching and amplifying applications where very  
low threshold voltage, high breakdown voltage, high input  
impedance, low input capacitance, and fast switching speeds  
are desired.  
Logic level interfaces - ideal for TTL and CMOS  
Solid state relays  
Analog switches  
Power management  
Telecom switches  
Ordering Information  
Product Summary  
RDS(ON)  
Part Number  
Package Option  
Packing  
VGS(th)  
(max)  
BVDSS/BVDGS  
(max)  
TP2104K1-G  
TO-236AB (SOT-23) 3000/Reel  
-40V  
6.0Ω  
-2.0V  
TP2104N3-G  
3-Lead TO-92  
1000/Bag  
2000/Reel  
TP2104N3-G P002  
TP2104N3-G P003  
Pin Configuration  
DRAIN  
TP2104N3-G P005 3-Lead TO-92  
TP2104N3-G P013  
TP2104N3-G P014  
DRAIN  
SOURCE  
GATE  
-G denotes a lead (Pb)-free / RoHS compliant package.  
Contact factory for Wafer / Die availablity.  
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.  
SOURCE  
GATE  
TO-236AB (SOT-23)  
TO-92  
Absolute Maximum Ratings  
Parameter  
Value  
BVDSS  
BVDGS  
±20V  
Product Marking  
Drain-to-source voltage  
Drain-to-gate voltage  
W = Code for week sealed  
= “Green” Packaging  
P1LW  
Gate-to-source voltage  
Package may or may not include the following marks: Si or  
Operating and storage temperature  
-55OC to +150OC  
TO-236AB (SOT-23)  
Absolute Maximum Ratings are those values beyond which damage to the device  
may occur. Functional operation under these conditions is not implied. Continuous  
operation of the device at the absolute rating level may affect device reliability. All  
voltages are referenced to device ground.  
SiTP  
2 1 0 4  
YYWW  
YY = Year Sealed  
WW = Week Sealed  
Typical Thermal Resistance  
= “Green” Packaging  
Package  
θja  
Package may or may not include the following marks: Si or  
203OC/W  
132OC/W  
TO-92  
TO-236AB (SOT-23)  
TO-92  
Doc.# DSFP-TP2104  
B081313  
Supertex inc.  
www.supertex.com  

TP2104K1-G 替代型号

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