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TP2104N3-G

更新时间： 2024-11-25 19:53:27
品牌 Logo 应用领域
超科 - SUPERTEX 开关晶体管
页数 文件大小 规格书
6页 567K
描述
Small Signal Field-Effect Transistor, 0.25A I(D), 40V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, TO-92, GREEN PACKAGE-3

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中文翻译

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TP2104N3-G 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Transferred零件包装代码：TO-92
包装说明：GREEN PACKAGE-3针数：3
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8541.21.00.95风险等级：7.88
其他特性：LOW THRESHOLD配置：SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：40 V最大漏极电流 (ID)：0.175 A
最大漏源导通电阻：6 ΩFET 技术：METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss)：10 pFJEDEC-95代码：TO-92
JESD-30 代码：O-PBCY-T3JESD-609代码：e3
元件数量：1端子数量：3
工作模式：ENHANCEMENT MODE最高工作温度：150 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装形状：ROUND封装形式：CYLINDRICAL
峰值回流温度（摄氏度）：NOT SPECIFIED极性/信道类型：P-CHANNEL
认证状态：Not Qualified表面贴装：NO
端子面层：Matte Tin (Sn)端子形式：THROUGH-HOLE
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

TP2104N3-G 数据手册

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TP2104  
P-Channel Enhancement Mode  
Vertical DMOS FETs  
Features  
General Description  
This low threshold enhancement-mode (normally-off)  
transistorutilizesaverticalDMOSstructureandSupertex’s  
well-proven silicon-gate manufacturing process. This  
combination produces a device with the power handling  
capabilities of bipolar transistors and with the high input  
impedance and positive temperature coefficient inherent  
in MOS devices. Characteristic of all MOS structures,  
this device is free from thermal runaway and thermally-  
induced secondary breakdown.  
► High input impedance and high gain  
► Low power drive requirement  
► Ease of paralleling  
► Low CISS and fast switching speeds  
► Excellent thermal stability  
► Integral source-drain diode  
► Free from secondary breakdown  
Applications  
Supertex’s vertical DMOS FETs are ideally suited to a wide  
range of switching and amplifying applications where very  
low threshold voltage, high breakdown voltage, high input  
impedance, low input capacitance, and fast switching  
speeds are desired.  
► Logic level interfaces - ideal for TTL and CMOS  
► Solid state relays  
► Analog switches  
► Power management  
► Telecom switches  
Ordering Information  
RDS(ON)  
VGS(th)  
Package Options  
BVDSS/BVDGS  
Device  
(max)  
(Ω)  
(max)  
(V)  
(V)  
TO-236AB (SOT-23)  
TO-92  
TP2104  
TP2104K1-G  
TP2104N3-G  
-40  
6.0  
-2.0  
-G indicates package is RoHS compliant (‘Green’)  
Pin Configuration  
DRAIN  
DRAIN  
SOURCE  
SOURCE  
Absolute Maximum Ratings  
Parameter  
GATE  
GATE  
Value  
BVDSS  
BVDGS  
±20V  
TO-92 (N3)  
TO-236AB (SOT-23) (K1)  
Drain-to-source voltage  
Drain-to-gate voltage  
Product Marking  
SiTP  
2 1 0 4  
Y Y WW  
YY = Year Sealed  
WW = Week Sealed  
= “Green” Packaging  
Gate-to-source voltage  
Operating and storage temperature  
Soldering temperature*  
-55°C to +150°C  
+300°C  
Package may or may not include the following marks: Si or  
TO-92 (N3)  
Absolute Maximum Ratings are those values beyond which damage to the device may  
occur. Functional operation under these conditions is not implied. Continuous operation  
of the device at the absolute rating level may affect device reliability. All voltages are  
referenced to device ground.  
W = Code for week sealed  
P1LW  
= “Green” Packaging  
*
Distance of 1.6mm from case for 10 seconds.  
Package may or may not include the following marks: Si or  
TO-236AB (SOT-23) (K1)  
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com  
123456

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