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TP2104N3-GP014 PDF预览

TP2104N3-GP014

更新时间： 2024-11-25 21:06:43
品牌 Logo 应用领域
美国微芯 - MICROCHIP 开关晶体管
页数 文件大小 规格书
6页 721K
描述
SMALL SIGNAL, FET

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中文翻译

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TP2104N3-GP014 技术参数

生命周期：Active包装说明：CYLINDRICAL, O-PBCY-T3
Reach Compliance Code：compliant风险等级：5.63
配置：SINGLE WITH BUILT-IN DIODE最小漏源击穿电压：40 V
最大漏极电流 (ID)：0.175 A最大漏源导通电阻：6 Ω
FET 技术：METAL-OXIDE SEMICONDUCTOR最大反馈电容 (Crss)：10 pF
JEDEC-95代码：TO-92JESD-30 代码：O-PBCY-T3
元件数量：1端子数量：3
工作模式：ENHANCEMENT MODE封装主体材料：PLASTIC/EPOXY
封装形状：ROUND封装形式：CYLINDRICAL
极性/信道类型：P-CHANNEL表面贴装：NO
端子形式：THROUGH-HOLE端子位置：BOTTOM
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

TP2104N3-GP014 数据手册

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Supertex inc.  
TP2104  
P-Channel Enhancement-Mode  
Vertical DMOS FET  
Features  
General Description  
► High input impedance and high gain  
► Low power drive requirement  
► Ease of paralleling  
This low threshold, enhancement-mode (normally-off) transistor  
utilizes a vertical DMOS structure and Supertex’s well-  
proven, silicon-gate manufacturing process. This combination  
produces a device with the power handling capabilities of  
bipolar transistors and the high input impedance and positive  
temperature coefficient inherent in MOS devices. Characteristic  
of all MOS structures, this device is free from thermal runaway  
and thermally-induced secondary breakdown.  
► Low CISS and fast switching speeds  
► Excellent thermal stability  
► Integral source-drain diode  
► Free from secondary breakdown  
Applications  
Supertex’s vertical DMOS FETs are ideally suited to a wide  
range of switching and amplifying applications where very  
low threshold voltage, high breakdown voltage, high input  
impedance, low input capacitance, and fast switching speeds  
are desired.  
► Logic level interfaces - ideal for TTL and CMOS  
► Solid state relays  
► Analog switches  
► Power management  
► Telecom switches  
Ordering Information  
Product Summary  
RDS(ON)  
Part Number  
Package Option  
Packing  
VGS(th)  
(max)  
BVDSS/BVDGS  
(max)  
TP2104K1-G  
TO-236AB (SOT-23) 3000/Reel  
-40V  
6.0Ω  
-2.0V  
TP2104N3-G  
3-Lead TO-92  
1000/Bag  
2000/Reel  
TP2104N3-G P002  
TP2104N3-G P003  
Pin Configuration  
DRAIN  
TP2104N3-G P005 3-Lead TO-92  
TP2104N3-G P013  
TP2104N3-G P014  
DRAIN  
SOURCE  
GATE  
-G denotes a lead (Pb)-free / RoHS compliant package.  
Contact factory for Wafer / Die availablity.  
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.  
SOURCE  
GATE  
TO-236AB (SOT-23)  
TO-92  
Absolute Maximum Ratings  
Parameter  
Value  
BVDSS  
BVDGS  
±20V  
Product Marking  
Drain-to-source voltage  
Drain-to-gate voltage  
W = Code for week sealed  
= “Green” Packaging  
P1LW  
Gate-to-source voltage  
Package may or may not include the following marks: Si or  
Operating and storage temperature  
-55OC to +150OC  
TO-236AB (SOT-23)  
Absolute Maximum Ratings are those values beyond which damage to the device  
may occur. Functional operation under these conditions is not implied. Continuous  
operation of the device at the absolute rating level may affect device reliability. All  
voltages are referenced to device ground.  
SiTP  
2 1 0 4  
YYWW  
YY = Year Sealed  
WW = Week Sealed  
Typical Thermal Resistance  
= “Green” Packaging  
Package  
θja  
Package may or may not include the following marks: Si or  
203OC/W  
132OC/W  
TO-92  
TO-236AB (SOT-23)  
TO-92  
Doc.# DSFP-TP2104  
B081313  
Supertex inc.  
www.supertex.com  
123456

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