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TNETA1500PCM

更新时间： 2024-11-06 11:58:39
品牌 Logo 应用领域
德州仪器 - TI ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路信息通信管理发射机接收机异步传输模式
页数 文件大小 规格书
29页 419K
描述
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER

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TNETA1500PCM 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：QFP, QFP144,1.2SQ针数：144
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.84应用程序：ATM;SDH;SONET
JESD-30 代码：S-PQFP-G144长度：28 mm
功能数量：1端子数量：144
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP144,1.2SQ封装形状：SQUARE
封装形式：FLATPACK峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
座面最大高度：4.1 mm子类别：ATM/SONET/SDH ICs
最大压摆率：0.18 mA标称供电电压：5 V
表面贴装：YES技术：BICMOS
电信集成电路类型：ATM/SONET/SDH TRANSCEIVER温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：28 mmBase Number Matches：1

TNETA1500PCM 数据手册

 浏览型号TNETA1500PCM的Datasheet PDF文件第2页浏览型号TNETA1500PCM的Datasheet PDF文件第3页浏览型号TNETA1500PCM的Datasheet PDF文件第4页浏览型号TNETA1500PCM的Datasheet PDF文件第5页浏览型号TNETA1500PCM的Datasheet PDF文件第6页浏览型号TNETA1500PCM的Datasheet PDF文件第7页 
TNETA1500  
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER  
SDNS021D – MARCH 1994 – REVISED JANUARY 1998  
Single-Chip Receiver/Transmitter for  
Generates Alarms for:  
Transporting 53-Byte ATM Cells Via  
STS-3c/STM-1 Frame (155.52 Mbit/s)  
– Loss of Incoming Serial Signal (LOS)  
– Out of Frame (OOF)  
– Loss of Frame (LOF)  
On-Chip Analog Phase-Locked Loop  
(APLL) Provides:  
– Recovery of Receive Clock From  
Incoming Serial-Data Stream  
– Transmit Clock Generation From  
External 19.44-MHz Clock Source  
– B1-Byte Parity Error (B1ERR)  
– Loss of ATM Cell Alignment (LOCA)  
– Line Far-End Receive Failure (LFERF)  
– Receive Loss of Pointer (LOP)  
– Line Alarm Indication Signal (LAIS)  
Meets ATM Forum ATM User-Network  
Interface Specification Requirement  
Inserts and Extracts ATM Cells Into/From  
SONET/SDH STS-3c/STM-1 SPE  
BiCMOS Device Packaged in a 144-Pin  
Plastic Quad Flat Package (PQFP) or a  
144-Pin Thin Quad Flat Package (TQFP)  
Detects Multiple-Bit Errors and Corrects  
Single-Bit Errors in the 5-Byte ATM  
Headers of Incoming ATM Cells  
description  
The synchronous optical network (SONET)/synchronous digital hierarchy (SDH) asynchronous transport mode  
(ATM) line-interface receiver/transmitter provides a single-chip implementation for transporting ATM cells over  
the SONET/SDH network at the STS-3c/STM-1 rate of 155.52 Mbit/s. This device provides all the functionality  
required to insert and extract 53-byte ATM cells into/from an STS-3c/STM-1 synchronous payload envelope  
(SPE), including clock recovery and clock generation using analog phase-locked loops (APLL).  
On the receive side, the TNETA1500 accepts 155.52-Mbit/s serial data, recovers the embedded clock signal,  
performs SONET/SDH frame alignment and serial-to-parallel conversion, identifies the SONET/SDH payload,  
and establishes the ATM-cell boundaries. The ATM cells are extracted from the payload, descrambled, and  
passed to the receive output FIFO for output to the next device (i.e., a reassembly device). On the transmit side,  
complete 53-byte ATM cells are placed into the transmit input FIFO, scrambled, and inserted into an  
STS-3c/STM-1 SPE. The SONET/SDH frame is scrambled and converted to a serial-data stream for output.  
An APLL is used to generate the 155.52-MHz output clock from a low-speed 19.44-MHz oscillator, eliminating  
the need for a high-speed 155.52-MHz oscillator.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...29

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