TNETA1575
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI-HOST AND COPROCESSOR INTERFACES
SDNS040C – MAY 1996 – REVISED JUNE 1998
Supports Segmentation and Reassembly of
Host Accesses to the PHY-Layer Device
Can Be Performed Indirectly via the
TNETA1575 Local Peripheral Bus
AAL5 Packets in Accordance With ITU-T
Specifications I.361 and I.363
(11/93 Update)
Local Peripheral Bus Maps the PHY Device
Into the TNETA1575 PCI-Bus Address
Space
Integrated 32-Bit PCI Bus 2.1 (06/95)
Interface for Transferring Packet Data to
and From Host Memory
Supports Easy Access to AAL5 Trailer
Information
Provides Simultaneous Segmentation of up
to 2048 Packets
Supports Buffer Scatter/Gather (Transmit
and Receive Buffer Chaining)
Provides Simultaneous Reassembly of up
to 2048 Packets
Optional Early Segmentation of Packets, So
Segmentation Begins Once a Transmit
Buffer Is Filled, Instead of Waiting for the
Entire Packet to Be Available in Host
Memory
Provides Full VPI/VCI Support (12 VPI Bits
and 16 VCI Bits) for Transmit and Receive
Operations
Supports Constant-Bit-Rate (CBR) Traffic
via High-Priority Mechanism or Local Static
Scheduler Table
Calculates the HEC Byte for the Header of
an Outgoing Cell
Backward Compatible With the TNETA1570
in 32-Bit PCI Mode
Checks the HEC Byte of an Incoming Cell
UTOPIA Level 1-Compliant Cell Interface
Internal 32-Cell Receive FIFO
Provides Support for Available-Bit-Rate
(ABR) Traffic via External Coprocessor
Interface (COPI)
Cell Interface Can Be Programmed to
Operate as Either a Physical (PHY-Layer)
Interface or as a SAR/Switch (ATM-Layer)
Interface
Provides Support for VBR-nrt Traffic via
External COPI
Transmit-Channel Sleep Mode Prevents the
SAR Polling Channels When No Packets
Are Queued
Provides Reassembly Time Out for
Incoming Packets
Provides an Internal Loopback Capability
From Transmit to Receive
High-Performance Features Include Use of
Sideband Signals to Reduce Polling Across
the PCI Bus
Supports Boundary Scan Through a
Five-Wire JTAG Interface in Accordance
With IEEE Std 1149.1-1990 (Includes IEEE
Std 1149.1a-1993)
description
The TNETA1575 is an asynchronous transfer mode (ATM) segmentation and reassembly (SAR) device with
a peripheral component interconnect (PCI)-bus interface and a coprocessor interface (COPI). The TNETA1575
continues the line of Texas Instruments (TI) ATM SAR devices directed toward the classical LAN-to-ATM
translation market segment. Features have been extended to include the COPI interface, which interfaces to
an external scheduler with high-performance features to eliminate polling on the PCI bus. The TNETA1575 is
designed for the emerging class of high-performance enterprise networking hubs that utilize ATM in the
backplane, in addition to the traditional frame-/packet-based bus systems. Some of the features required for
this application include: high level of virtual channel/virtual path support, support for isochronous services, early
segmentation, and high-performance, 32-bit PCI-bus support. The feature set required by cell-operating
enterprisehubsisdifferentfromthesetsbeingofferedbyotherSARdevices, whicharedirectedprimarilytoward
the adapter card market.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Thundercell and TI are trademarks of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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