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TNETA1500APGE

更新时间： 2024-11-24 02:58:43
品牌 Logo 应用领域
德州仪器 - TI ATM异步传输模式
页数 文件大小 规格书
29页 425K
描述
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER

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TNETA1500APGE 数据手册

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TNETA1500A  
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER  
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998  
Single-Chip Receiver/Transmitter for  
Generates Alarms for:  
Transporting 53-Byte Asynchronous  
Transport Mode (ATM) Cells Via  
STS-3c/STM-1 Frame (155.52 Mbit/s)  
– Loss of Incoming Serial Signal (LOS)  
– Out of Frame (OOF)  
– Loss of Frame (LOF)  
– B1-Byte Parity Error (B1ERR)  
– Loss of ATM Cell Alignment (LOCA)  
– Line Far-End Receive Failure (LFERF)  
– Receive Loss of Pointer (LOP)  
– Line Alarm Indication Signal (LAIS)  
On-Chip Analog Phase-Locked Loop  
(APLL) Provides:  
– Recovery of Receive Clock From  
Incoming Serial-Data Stream  
– Transmit Clock Generation From  
External 19.44-MHz Clock Source  
Meets ATM Forum ATM User-Network  
Interface Specification Requirement  
Inserts and Extracts ATM Cells Into/From  
SONET/SDH STS-3c/STM-1 SPE  
Package Options Include 144-Pin Plastic  
Quad Flat (PCM) and 144-Pin Thin Quad  
Flat (PGE) Packages  
Detects Multiple-Bit Errors and Corrects  
Single-Bit Errors in the 5-Byte ATM  
Headers of Incoming ATM Cells  
description  
The synchronous optical network (SONET)/synchronous digital hierarchy (SDH) asynchronous transport mode  
(ATM) line-interface receiver/transmitter provides a single-chip implementation for transporting ATM cells over  
the SONET/SDH network at the STS-3c/STM-1 rate of 155.52 Mbits/s. This device provides all the functionality  
required to insert and extract 53-byte ATM cells into/from an STS-3c/STM-1 synchronous payload envelope  
(SPE), including clock recovery and clock generation using analog phase-locked loops (APLL).  
On the receive side, the TNETA1500A accepts 155.52-Mbit/s serial data, recovers the embedded clock signal,  
performs SONET/SDH frame alignment and serial-to-parallel conversion, identifies the SONET/SDH payload,  
and establishes the ATM-cell boundaries. The ATM cells are extracted from the payload, descrambled, and  
passed to the receive output FIFO for output to the next device (i.e., a reassembly device). On the transmit side,  
complete 53-byte ATM cells are placed in the transmit input FIFO, scrambled, and inserted into an  
STS-3c/STM-1 SPE. The SONET/SDH frame is scrambled and converted to a serial-data stream for output.  
An APLL is used to generate the 155.52-MHz output clock from a low-speed 19.44-MHz oscillator, eliminating  
the need for a high-speed 155.52-MHz oscillator.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...29

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