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TMS320C6424AZWT600 PDF预览

TMS320C6424AZWT600

更新时间： 2024-10-29 06:08:07
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德州仪器 - TI /
页数 文件大小 规格书
239页 2017K
描述
IC,DSP,32-BIT,CMOS,BGA,361PIN,PLASTIC

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TMS320C6424AZWT600 数据手册

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TMS320C6424  
Fixed-Point Digital Signal Processor  
www.ti.com  
SPRS347–MARCH 2007  
1 TMS320C6424 Fixed-Point Digital Signal Processor  
1.1 Features  
[Flexible Allocation]  
1M-Bit (128K-Byte) L2 Unified Mapped  
RAM/Cache [Flexible Allocation]  
•
High-Performance Digital Signal Processor  
(C6424)  
–
–
–
–
–
–
–
2.5-, 2-, 1.67-ns Instruction Cycle Time  
400-, 500-, 600-MHz C64x+™ Clock Rate  
Eight 32-Bit C64x+ Instructions/Cycle  
3200, 4000, 4800 MIPS  
Fully Software-Compatible With C64x  
Commercial and Extended Temperature  
Ranges  
•
•
Endianess: Supports Both Little Endian and  
Big Endian  
External Memory Interfaces (EMIFs)  
–
32-Bit DDR2 SDRAM Memory Controller  
With 256M-Byte Address Space (1.8-V I/O)  
Asynchronous 16-Bit Wide EMIF (EMIFA)  
With up to 128M-Byte Address Reach  
–
•
VelociTI.2™ Extensions to VelociTI™  
Advanced Very-Long-Instruction-Word (VLIW)  
TMS320C64x+™ DSP Core  
•
Flash Memory Interfaces  
•
•
NOR (8-/16-Bit-Wide Data)  
NAND (8-/16-Bit-Wide Data)  
–
Eight Highly Independent Functional Units  
With VelociTI.2 Extensions:  
•
•
Enhanced Direct-Memory-Access (EDMA)  
Controller (64 Independent Channels)  
•
Six ALUs (32-/40-Bit), Each Supports  
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit  
Arithmetic per Clock Cycle  
Two 64-Bit General-Purpose Timers (Each  
Configurable as Two 32-Bit Timers)  
•
Two Multipliers Support Four 16 x 16-Bit  
Multiplies (32-Bit Results) per Clock  
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit  
Results) per Clock Cycle  
•
•
One 64-Bit Watch Dog Timer  
Two UARTs (One with RTS and CTS Flow  
Control)  
–
Load-Store Architecture With Non-Aligned  
Support  
64 32-Bit General-Purpose Registers  
Instruction Packing Reduces Code Size  
All Instructions Conditional  
•
•
Master/Slave Inter-Integrated Circuit (I2C  
Bus™)  
–
–
–
–
Two Multichannel Buffered Serial Ports  
(McBSPs)  
–
–
–
–
–
–
I2S and TDM  
AC97 Audio Codec Interface  
SPI  
Standard Voice Codec Interface (AIC12)  
Telecom Interfaces – ST-Bus, H-100  
128 Channel Mode  
Additional C64x+™ Enhancements  
•
•
Protected Mode Operation  
Exceptions Support for Error Detection  
and Program Redirection  
•
Hardware Support for Modulo Loop  
Auto-Focus Module Operation  
•
Multichannel Audio Serial Port (McASP0)  
Four Serializers and SPDIF (DIT) Mode  
•
C64x+ Instruction Set Features  
–
–
–
–
–
–
–
Byte-Addressable (8-/16-/32-/64-Bit Data)  
8-Bit Overflow Protection  
Bit-Field Extract, Set, Clear  
Normalization, Saturation, Bit-Counting  
VelociTI.2 Increased Orthogonality  
C64x+ Extensions  
•
•
16-Bit Host-Port Interface (HPI)  
32-Bit 33-MHz, 3.3-V Peripheral Component  
Interconnect (PCI) Master/Slave Interface  
Conforms to PCI Specification 2.3  
•
10/100 Mb/s Ethernet MAC (EMAC)  
–
–
IEEE 802.3 Compliant  
Supports Multiple Media Independent  
Interfaces (MII, RMII)  
•
•
Compact 16-bit Instructions  
Additional Instructions to Support  
Complex Multiplies  
–
Management Data Input/Output (MDIO)  
Module  
•
C64x+ L1/L2 Memory Architecture  
–
256K-Bit (32K-Byte) L1P Program  
RAM/Cache [Flexible Allocation]  
640K-Bit (80K-Byte) L1D Data RAM/Cache  
•
•
VLYNQ™ Interface (FPGA Interface)  
Three Pulse Width Modulator (PWM) Outputs  
–
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this document.  
All trademarks are the property of their respective owners.  
PRODUCT PREVIEW information concerns products in the  
formative or design phase of development. Characteristic data and  
other specifications are design goals. Texas Instruments reserves  
the right to change or discontinue these products without notice.  
Copyright © 2007, Texas Instruments Incorporated  
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