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TMS320C6424Q

更新时间： 2024-10-29 11:07:11
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德州仪器 - TI 双倍数据速率控制器微控制器微控制器和处理器数字信号处理器
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247页 1246K
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C64x+ 定点 DSP- 高达 600MHz、16/8 位 EMIFA、32/16 位 DDR2

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TMS320C6424Q 数据手册

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TMS320C6424  
www.ti.com  
SPRS347D–MARCH 2007–REVISED DECEMBER 2009  
TMS320C6424 Fixed-Point Digital Signal Processor  
Check for Samples: TMS320C6424  
1 TMS320C6424 Fixed-Point Digital Signal Processor  
1.1 Features  
1
• High-Performance Digital Signal Processor  
(C6424)  
• C64x+ L1/L2 Memory Architecture  
– 256K-Bit (32K-Byte) L1P Program  
RAM/Cache [Flexible Allocation]  
– 640K-Bit (80K-Byte) L1D Data RAM/Cache  
[Flexible Allocation]  
– 1M-Bit (128K-Byte) L2 Unified Mapped  
RAM/Cache [Flexible Allocation]  
– 2.5-, 2-, 1.67-, 1.43-ns Instruction Cycle Time  
– 400-, 500-, 600-, 700-MHz C64x+™ Clock Rate  
– Eight 32-Bit C64x+ Instructions/Cycle  
– 3200, 4000, 4800, 5600 MIPS  
– Fully Software-Compatible With C64x  
– Commercial and Automotive (Q or S suffix)  
Grades  
• Endianess: Supports Both Little Endian and  
Big Endian  
• External Memory Interfaces (EMIFs)  
– Low-Power Device (L suffix)  
– 32-Bit DDR2 SDRAM Memory Controller With  
256M-Byte Address Space (1.8-V I/O)  
• VelociTI.2™ Extensions to VelociTI™  
Advanced Very-Long-Instruction-Word (VLIW)  
TMS320C64x+™ DSP Core  
•
Supports up to 333-MHz (data rate) bus  
and interfaces to DDR2-400 SDRAM  
– Eight Highly Independent Functional Units  
With VelociTI.2 Extensions:  
– Asynchronous 16-Bit Wide EMIF (EMIFA)  
With up to 128M-Byte Address Reach  
•
Six ALUs (32-/40-Bit), Each Supports  
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit  
Arithmetic per Clock Cycle  
•
Flash Memory Interfaces  
–
–
NOR (8-/16-Bit-Wide Data)  
NAND (8-/16-Bit-Wide Data)  
•
Two Multipliers Support Four 16 x 16-Bit  
Multiplies (32-Bit Results) per Clock  
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit  
Results) per Clock Cycle  
• Enhanced Direct-Memory-Access (EDMA)  
Controller (64 Independent Channels)  
• Two 64-Bit General-Purpose Timers (Each  
Configurable as Two 32-Bit Timers)  
– Load-Store Architecture With Non-Aligned  
Support  
– 64 32-Bit General-Purpose Registers  
– Instruction Packing Reduces Code Size  
– All Instructions Conditional  
• One 64-Bit Watch Dog Timer  
• Two UARTs (One with RTS and CTS Flow  
Control)  
• Master/Slave Inter-Integrated Circuit (I2C Bus™)  
– Additional C64x+™ Enhancements  
• Two Multichannel Buffered Serial Ports  
(McBSPs)  
•
•
Protected Mode Operation  
Exceptions Support for Error Detection  
and Program Redirection  
– I2S and TDM  
– AC97 Audio Codec Interface  
– SPI  
– Standard Voice Codec Interface (AIC12)  
– Telecom Interfaces – ST-Bus, H-100  
– 128 Channel Mode  
•
Hardware Support for Modulo Loop  
Auto-Focus Module Operation  
• C64x+ Instruction Set Features  
– Byte-Addressable (8-/16-/32-/64-Bit Data)  
– 8-Bit Overflow Protection  
• Multichannel Audio Serial Port (McASP0)  
– Four Serializers and SPDIF (DIT) Mode  
• 16-Bit Host-Port Interface (HPI)  
• 32-Bit 33-MHz, 3.3-V Peripheral Component  
Interconnect (PCI) Master/Slave Interface  
– Bit-Field Extract, Set, Clear  
– Normalization, Saturation, Bit-Counting  
– VelociTI.2 Increased Orthogonality  
– C64x+ Extensions  
•
•
Compact 16-bit Instructions  
Additional Instructions to Support  
Complex Multiplies  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007–2009, Texas Instruments Incorporated  
 
 
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