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TMS320C6452

更新时间: 2024-10-28 11:58:23
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TMS320C6452 Digital Signal Processor

TMS320C6452 数据手册

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TMS320C6452  
www.ti.com  
SPRS371F OCTOBER 2007REVISED APRIL 2012  
TMS320C6452 Digital Signal Processor  
Check for Samples: TMS320C6452  
1 Features  
1
– 256K-bit (32K-byte) L1P Program RAM/Cache  
[Direct Mapped]  
– 256K-bit (32K-byte) L1D Data RAM/Cache  
[2-Way Set-Associative]  
– 1408KB L2 Unified Mapped RAM/Cache  
[Flexible Allocation]  
• High-Performance Digital Media Processor  
– 720-MHz, 900-MHz C64x+™ Clock Rates  
– 1.39 ns (-720), 1.11 ns (-900) Instruction  
Cycle Time  
– 5760, 7200 MIPS  
– Eight 32-Bit C64x+ Instructions/Cycle  
– Fully Software-Compatible With C64x/Debug  
– Commercial Temperature Ranges (-720, -900  
only)  
• Supports Little Endian Mode Only  
• External Memory Interfaces (EMIFs)  
– 32-Bit DDR2 SDRAM Memory Controller With  
512M-Byte Address Space (1.8-V I/O)  
– Asynchronous 16-Bit Wide EMIF (EMIFA)  
– Industrial Temperature Ranges (-720, -900  
only)  
Up to 128M-Byte Total Address Reach  
64M-Byte Address Reach per CE Space  
• VelociTI.2™ Extensions to VelociTI™  
Advanced Very-Long-Instruction-Word (VLIW)  
TMS320C64x+™ DSP Core  
– Glueless Interface to Asynchronous  
Memories (SRAM, Flash, and EEPROM)  
– Synchronous Memories (SBSRAM and ZBT  
SRAM)  
– Supports Interface to Standard Sync Devices  
and Custom Logic (FPGA, CPLD, ASICs,  
etc.)  
– Eight Highly Independent Functional Units  
With VelociTI.2 Extensions:  
Six ALUs (32-/40-Bit), Each Supports  
Single 32-bit, Dual 16-bit, or Quad 8-bit  
Arithmetic per Clock Cycle  
Two Multipliers Support Four 16 x 16-bit  
Multiplies (32-bit Results) per Clock Cycle  
or Eight 8 x 8-bit Multiplies (16-Bit  
Results) per Clock Cycle  
• Enhanced Direct-Memory-Access (EDMA)  
Controller (64 Independent Channels)  
• 3-Port Gigabit Ethernet Switch Subsystem  
– Load-Store Architecture With Non-Aligned  
Support  
• Four 64-Bit General-Purpose Timers (Each  
Configurable as Two 32-Bit Timers)  
– 64 32-bit General-Purpose Registers  
– Instruction Packing Reduces Code Size  
– All Instructions Conditional  
• One UART (With RTS and CTS Flow Control)  
• One 4-wire Serial Port Interface (SPI) With Two  
Chip-Selects  
– Additional C64x+™ Enhancements  
• Master/Slave Inter-Integrated Circuit (I2C  
Bus™)  
• Two Telecom Serial Interface Ports (TSIP0/1)  
• Multichannel Audio Serial Port (McASP)  
– Ten Serializers and SPDIF (DIT) Mode  
• 16/32-Bit Host-Port Interface (HPI)  
Protected Mode Operation  
Exceptions Support for Error Detection  
and Program Redirection  
Hardware Support for Modulo Loop Auto-  
Focus Module Operation  
• C64x+ Instruction Set Features  
– Byte-Addressable (8-/16-/32-/64-bit Data)  
– 8-bit Overflow Protection  
• Advanced Event Triggering (AET) Compatible  
• 32-Bit 33-/66-MHz, 3.3-V Peripheral Component  
Interconnect (PCI) Master/Slave Interface  
Conforms to PCI Specification 2.3  
– Bit-Field Extract, Set, Clear  
• VLYNQ™ Interface (FPGA Interface)  
• On-Chip ROM Bootloader  
• Individual Power-Saving Modes  
• Flexible PLL Clock Generators  
• IEEE-1149.1 (JTAG™) Boundary-Scan-  
Compatible  
– Normalization, Saturation, Bit-Counting  
– VelociTI.2 Increased Orthogonality  
– C64x+ Extensions  
Compact 16-bit Instructions  
Additional Instructions to Support  
Complex Multiplies  
• 32 General-Purpose I/O (GPIO) Pins  
• C64x+ L1/L2 Memory Architecture  
(Multiplexed With Other Device Functions)  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date. Products conform to  
specifications per the terms of the Texas Instruments standard warranty. Production  
processing does not necessarily include testing of all parameters.  
Copyright © 2007–2012, Texas Instruments Incorporated  
 

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