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TM2EJ64DPN PDF预览

TM2EJ64DPN

更新时间: 2024-11-25 12:22:27
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
20页 312K
描述
EXTENDED-DATA-OUT DYNAMIC RAM MODULES ─ SODIMM

TM2EJ64DPN 数据手册

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ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈꢉꢊ ꢀ ꢁꢂ ꢋ ꢄ ꢅ ꢆ ꢇꢈꢉ ꢂ ꢌ ꢍ ꢎꢏ ꢌ ꢐ ꢑ ꢂ ꢒ ꢓ ꢅꢆ ꢔꢒ ꢕ ꢀ  
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢈꢉꢊ ꢀ ꢁꢂ ꢋ ꢄ ꢅ ꢆ ꢃꢈ ꢉ ꢂ ꢌ ꢍ ꢎꢏ ꢌ ꢐ ꢑ ꢂ ꢒ ꢓ ꢅꢆ ꢔꢒ ꢕ ꢀ  
SMMS685 − AUGUST 1997  
D
D
D
Organization  
− TM2xJ64xPN-xx . . . 2097152 × 64 Bits  
Single 3.3-V Power Supply  
( 10% Tolerance)  
D
D
High-Speed, Low-Noise LVTTL Interface  
Long Refresh Period:  
− TM2EJ64DPN: 32 ms (2048 cycles)  
− TM2EJ64EPN: 64 ms (4096 cycles)  
JEDEC 144-Pin Small Outline Dual-In-Line  
Memory Module (SODIMM) Without Buffer  
for Use With Socket  
D
Low-Power, Battery-Backup Refresh  
Available:  
− TM2FJ64DPN: 128 ms (2048 cycles)  
− TM2FJ64EPN: 128 ms (4096 cycles)  
D
D
TM2xJ64xPN-xx — Utilizes Eight 16M-Bit  
(2M×8-Bit) Dynamic RAMs in TSOPs  
Performance ranges  
D
D
3-State Output  
Extended-Data-Out (EDO) Operation With  
CAS-Before-RAS (CBR), RAS-Only, and  
Hidden Refresh  
ACCESS ACCESS ACCESS  
TIME TIME TIME  
EDO  
CYCLE  
t
t
t
t
RAC  
CAC  
AA  
HPC  
D
D
D
Serial Presence-Detect (SPD) Using  
EEPROM  
MAX  
50 ns  
60 ns  
70 ns  
MAX  
13 ns  
15 ns  
18 ns  
MAX  
25 ns  
30 ns  
35 ns  
MIN  
’2xJ64xPN-50  
’2xJ64xPN-60  
’2xJ64xPN-70  
20 ns  
25 ns  
30 ns  
Ambient Temperature Range  
0°C to 70°C  
Gold-Plated Contacts  
description  
The TM2EJ64DPN is a 16M-byte, 144-pin, small outline dual-in-line memory module (SODIMM). The SODIMM  
is composed of eight TMS427809A, 2097152 × 8-bit 2K-refresh EDO dynamic random-access memories  
(DRAMs), each in a 400-mil, 28-pin plastic thin small-outline package (TSOP) (DGC suffix) mounted on a  
substrate with decoupling capacitors. See the TMS427809A data sheet (literature number SMKS894).  
The TM2EJ64EPN is an 16M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS426809A,  
2097152 × 8-bit 4K-refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP (DGC suffix) mounted on a  
substrate with decoupling capacitors. See the TMS426809A data sheet (literature number SMKS894).  
The TM2FJ64DPN is a 16M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS427809AP,  
2097152 × 8-bit 2K low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP  
(DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS427809AP data sheet (literature  
number SMKS894).  
The TM2FJ64EPN is a 16M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS426809AP,  
2097152 × 8-bit 4K low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP  
(DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS426809AP data sheet (literature  
number SMKS894).  
operation  
The TM2xJ64xPN operates as eight TMS42x809A/Ps, connected as shown in the functional block diagram.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢭꢪ ꢫ ꢡ ꢱꢢ ꢬꢯ ꢧ ꢫ ꢪ ꢤꢣ ꢭꢪ ꢰ ꢪ ꢲꢤ ꢬꢦꢪ ꢢꢨꢳ ꢚ ꢯꢧ ꢥꢧ ꢩꢨ ꢪꢥ ꢡꢫ ꢨꢡ ꢩ ꢭꢧ ꢨꢧ ꢧꢢ ꢭ ꢤꢨ ꢯꢪꢥ  
Copyright 1997, Texas Instruments Incorporated  
ꢩ ꢯꢧ ꢢ ꢱꢪ ꢤꢥ ꢭꢡ ꢫ ꢩ ꢤꢢ ꢨꢡ ꢢꢮꢪ ꢨ ꢯꢪ ꢫ ꢪ ꢬꢥ ꢤꢭ ꢮꢩꢨ ꢫ ꢵ ꢡꢨꢯ ꢤꢮꢨ ꢢꢤꢨ ꢡꢩꢪ ꢳ  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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