ꢀ
ꢁ
ꢂ
ꢂ
ꢃ
ꢃ
ꢄ
ꢄ
ꢅ
ꢅ
ꢆ
ꢆ
ꢃ
ꢇ
ꢈ
ꢈ
ꢉ
ꢉ
ꢊ
ꢊ
ꢀ
ꢁ
ꢂ
ꢂ
ꢋ
ꢋ
ꢄ
ꢄ
ꢅ
ꢆ
ꢆ
ꢃ
ꢇ
ꢈ
ꢈ
ꢉ
ꢉ
ꢂ
ꢂ
ꢍ ꢎ ꢏ ꢐ ꢑ ꢂ ꢒ ꢓ ꢅ ꢆ ꢔꢒꢕ ꢀ
ꢍ ꢎ ꢏ ꢐ ꢑ ꢂ ꢒ ꢓ ꢅ ꢆ ꢔꢒꢕ ꢀ
ꢀ
ꢁ
ꢀꢁ
ꢅ
ꢃ ꢖꢀ ꢃꢉ ꢇ ꢃꢇ ꢔꢇ ꢗꢀꢗꢔꢘ ꢙꢀ ꢇꢓ ꢉꢗ ꢁꢕ ꢚ ꢛꢗ ꢁ ꢁ ꢘꢇ ꢙꢜ ꢃꢝ ꢞ ꢝꢘ ꢇꢕ ꢁꢁ
SMMS685 − AUGUST 1997
small outline dual-in-line memory module and components
The small−outline dual-in-line memory module and components include:
D
D
D
PC substrate: 1,10 " 0,1 mm (0.04 inch) nominal thickness
Bypass capacitors: Multilayer ceramic
Contact area: Nickel plate and gold plate over copper
functional block diagram for the TM2xJ64xPN
RAS0
WE0
OE0
RAS0
WE0
OE0
CAS0
CAS OE W RAS
CAS4
CAS OE W RAS
DQ[0:7]
DQ[0:7]
U0
DQ[32:39]
DQ[0:7]
UB0
CAS1
CAS OE W RAS
CAS5
CAS OE W RAS
DQ[8:15]
DQ[0:7]
U1
DQ[40:47]
DQ[0:7]
UB1
CAS6
CAS OE W RAS
CAS2
CAS OE W RAS
DQ[48:55]
DQ[0:7]
UB2
DQ[16:23]
DQ[0:7]
U2
CAS7
CAS OE W RAS
CAS3
CAS OE W RAS
DQ[56:63]
DQ[0:7]
UB3
DQ[24:31]
DQ[0:7]
U3
TM2xJ64DPN:
A[0:10]
SPD EEPROM
A[0:10] : U[0:3], UB[0:3]
A[0:11] : U[0:3], UB[0:3]
SCL
SDA
A0
A1
A2
TM2xJ64EPN:
A[0:11]
V
SS
V
DD
U[0:3], UB[0:3]
Two 0.1 µF
(minimum) per
DRAM
V
SS
U[0:3], UB[0:3]
4
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