ꢀ
ꢁ
ꢂ
ꢂ
ꢃ
ꢃ
ꢄ
ꢄ
ꢅ
ꢅ
ꢆ
ꢆ
ꢃ
ꢇ
ꢈ
ꢈ
ꢉ
ꢉ
ꢊ
ꢊ
ꢀ
ꢁ
ꢂ
ꢂ
ꢋ
ꢋ
ꢄ
ꢄ
ꢅ
ꢆ
ꢆ
ꢃ
ꢇ
ꢈ
ꢈ
ꢉ
ꢉ
ꢂ
ꢂ
ꢍ ꢎ ꢏ ꢐ ꢑ ꢂ ꢒ ꢓ ꢅ ꢆ ꢔꢒꢕ ꢀ
ꢍ ꢎ ꢏ ꢐ ꢑ ꢂ ꢒ ꢓ ꢅ ꢆ ꢔꢒꢕ ꢀ
ꢀ
ꢁ
ꢀꢁ
ꢅ
ꢃ ꢖꢀ ꢃꢉ ꢇ ꢃꢇ ꢔꢇ ꢗꢀꢗꢔꢘ ꢙꢀ ꢇꢓ ꢉꢗ ꢁꢕ ꢚ ꢛꢗ ꢁ ꢁ ꢘꢇ ꢙꢜ ꢃꢝ ꢞ ꢝꢘ ꢇꢕ ꢁꢁ
SMMS685 − AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted)
TM2EJ64DPN
’2EJ64DPN-50
’2EJ64DPN-60
’2EJ64DPN-70
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
I
I
I
I
= − 2 mA
= − 100 µA
= 2 mA
LVTTL
2.4
2.4
2.4
High-level output
voltage
OH
OH
OL
OL
V
V
V
OH
LVCMOS
LVTTL
V
−0.2
V
−0.2
V
−0.2
DD
DD
DD
0.4
0.2
0.4
0.2
0.4
0.2
Low-level output
voltage
V
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
I
DD
DD
All others = 0 V to V
I
I
10
10
10
10
10
10
µA
µA
I
Output current
(leakage)
V
= 3.6 V,
V
O
= 0 V to V ,
DD
DD
CASx high
O
Read- or
write-cycle
current
‡§
I
V
V
= 3.6 V,
Minimum cycle
960
16
8
800
16
8
720
16
8
mA
mA
mA
CC1
DD
= 2 V (LVTTL),
IH
After one memory cycle,
RAS0 and CASx high
I
Standby current
CC2
V
IH
= V − 0.2 V (LVCMOS),
DD
After one memory cycle,
RAS0 and CASx high
Average refresh
current
(RAS-only
V
= 3.6 V,
Minimum cycle,
DD
RAS0 cycling,
‡§
‡¶
I
I
960
880
800
720
720
640
mA
mA
CC3
CASx high (RAS-only refresh),
RAS0 low after CASx low (CBR)
refresh or CBR)
Average EDO
current
V
= 3.6 V,
t
= MIN,
DD
RAS0 low,
HPC
CASx cycling
CC4
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS0 = V
Measured with a maximum of one address change during each EDO cycle, t
IL
HPC
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443