Datasheet > TM2EJ64DPN

TM2EJ64DPN

更新时间： 2022-03-30 15:28:38

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
20页	312K
描述
EXTENDED-DATA-OUT DYNAMIC RAM MODULES â SODIMM

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SMMS685 − AUGUST 1997

electrical characteristics over recommended ranges of supply voltage and ambient temperture

(unless otherwise noted) (continued)

TM2FJ64DPN

’2FJ64DPN-50

’2FJ64DPN-60

’2FJ64DPN-70

†

PARAMETER

UNIT

TEST CONDITIONS

MIN

MAX

MIN

MAX

MIN

MAX

= − 2 mA

= − 100 µA

= 2 mA

LVTTL

2.4

High-level output

voltage

LVCMOS

LVTTL

−0.2

0.4

0.2

0.4

0.2

0.4

0.2

Low-level output

voltage

= 100 µA

LVCMOS

Input current

(leakage)

= 3.6 V,

V = 0 V to 3.9 V,

All others = 0 V to V

µA

Output current

(leakage)

= 3.6 V,

= 0 V to V ,

CASx high

Read- or

write-cycle

current

‡§

= 3.6 V,

Minimum cycle

960

800

720

CC1

= 2 V (LVTTL),

After one memory cycle,

RAS0 and CASx high

Standby current

CC2

= V − 0.2 V (LVCMOS),

After one memory cycle,

RAS0 and CASx high

1.2

Average refresh

current

(RAS-only

= 3.6 V,

Minimum cycle,

RAS0 cycling,

‡§

‡¶

960

800

720

CC3

CASx high (RAS-only refresh),

RAS0 low after CASx low (CBR)

refresh or CBR)

Average EDO

current

= 3.6 V,

= MIN,

HPC

880

1.6

720

1.6

640

1.6

CC4

RAS0 low,

CASx cycling

Average

self-refresh

current

CASx < 0.2 V,

Measured after t

RAS0 < 0.2 V,

CC6

min

RASS

Average battery

back-up

= 31.25 µs,

≤ 300 ns

RAS

operating current

(equivalent

refresh time is

128 ms), CBR

only

− 0.2 V ≤ V ≤ 3.9 V,

0 V ≤ V ≤ 0.2 V, WE0 and OE0 =

2.8

CC10

Address and data stable

†

For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.

Measured with outputs open

‡

Measured with a maximum of one address change while RAS0 = V

Measured with a maximum of one address change during each EDO cycle, t

HPC

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

1...5 6 789 10 11...20

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