ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈꢉꢊ ꢀ ꢁꢂ ꢋ ꢄ ꢅ ꢆ ꢇꢈꢉ ꢂ ꢌ ꢍ ꢎꢏ ꢌ ꢐ ꢑ ꢂ ꢒ ꢓ ꢅꢆ ꢔꢒ ꢕ ꢀ
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢈꢉꢊ ꢀ ꢁꢂ ꢋ ꢄ ꢅ ꢆ ꢃꢈ ꢉ ꢂ ꢌ ꢍ ꢎꢏ ꢌ ꢐ ꢑ ꢂ ꢒ ꢓ ꢅꢆ ꢔꢒ ꢕ ꢀ
ꢃ ꢖꢀ ꢃ ꢉꢇꢃꢇ ꢔꢇꢗꢀꢗꢔꢘ ꢙꢀ ꢇꢓꢉ ꢗꢁ ꢕꢚ ꢛꢗꢁ ꢁ ꢘꢇ ꢙꢜ ꢃꢝ ꢞ ꢝ ꢘ ꢇꢕ ꢁ ꢁ
SMMS685 − AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TM2FJ64EPN
’2FJ64EPN-50
’2FJ64EPN-60
’2FJ64EPN-70
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
I
I
I
I
= − 2 mA
= − 100 µA
= 2 mA
LVTTL
2.4
2.4
2.4
High-level output
voltage
OH
OH
OL
OL
V
V
V
OH
LVCMOS
LVTTL
V
−0.2
V
−0.2
V
−0.2
DD
DD
DD
0.4
0.2
0.4
0.2
0.4
0.2
Low-level output
voltage
V
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
I
DD
DD
All others = 0 V to V
I
I
10
10
10
10
10
10
µA
µA
I
Output current
(leakage)
V
= 3.6 V,
V
O
= 0 V to V ,
DD
DD
CASx high
O
Read- or
write-cycle
current
‡§
I
V
V
= 3.6 V,
Minimum cycle
720
8
560
8
480
8
mA
mA
mA
CC1
DD
= 2 V (LVTTL),
IH
After one memory cycle,
RAS0 and CASx high
I
Standby current
CC2
V
IH
= V − 0.2 V (LVCMOS),
DD
After one memory cycle,
RAS0 and CASx high
1.2
1.2
1.2
Average refresh
current
(RAS-only
V
= 3.6 V,
Minimum cycle,
DD
RAS0 cycling,
‡§
‡¶
I
720
560
480
mA
CC3
CASx high (RAS-only refresh),
RAS0 low after CASx low (CBR)
refresh or CBR)
Average EDO
current
V
DD
= 3.6 V,
t
= MIN,
HPC
I
I
800
2
720
2
640
2
mA
mA
CC4
RAS0 low,
CASx cycling
Average
self-refresh
current
CASx < 0.2 V,
Measured after t
RAS0 < 0.2 V,
CC6
min
RASS
Average battery
back-up
t
= 31.25 µs,
t
≤ 300 ns
RC
RAS
operating current
(equivalent
refresh time is
128 ms), CBR
only
V
− 0.2 V ≤ V ≤ 3.9 V,
DD
IH
0 V ≤ V ≤ 0.2 V, WE0 and OE0 =
I
2.8
2.8
2.8
mA
IL
CC10
V
,
IH
Address and data stable
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS0 = V
Measured with a maximum of one address change during each EDO cycle, t
IL
HPC
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443