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SY10E256JZ PDF预览

SY10E256JZ

更新时间: 2024-09-28 04:50:11
品牌 Logo 应用领域
麦瑞 - MICREL /
页数 文件大小 规格书
4页 63K
描述
3-BIT 4:1 MUX-LATCH

SY10E256JZ 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:LEAD FREE, PLASTIC, LCC-28针数:28
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.7其他特性:THREE 4:1 MUX FOLLOWED BY LATCH
系列:10EJESD-30 代码:S-PQCC-J28
JESD-609代码:e3长度:11.48 mm
逻辑集成电路类型:D LATCH位数:3
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:
输出特性:OPEN-EMITTER输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
传播延迟(tpd):0.8 ns认证状态:Not Qualified
座面最大高度:4.57 mm表面贴装:YES
技术:ECL温度等级:COMMERCIAL EXTENDED
端子面层:MATTE TIN端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
触发器类型:LOW LEVEL宽度:11.48 mm
Base Number Matches:1

SY10E256JZ 数据手册

 浏览型号SY10E256JZ的Datasheet PDF文件第2页浏览型号SY10E256JZ的Datasheet PDF文件第3页浏览型号SY10E256JZ的Datasheet PDF文件第4页 
3-BIT 4:1  
SY10E256  
SY100E256  
MUX-LATCH  
DESCRIPTION  
FEATURES  
950ps max. data to output  
The SY10/100E256 offer three 4:1 multiplexers followed  
by latches with differential outputs designed for use in new,  
high-performance ECL systems. Separate Select controls  
are provided for the leading 2:1 mux pairs (see block  
diagram).  
Extended 100E VEE range of –4.2V to –5.5V  
850ps max. latch enable to output  
Separate select controls  
Differential outputs  
When the Latch Enable (LEN) is at a logic LOW, the latch  
istransparentandoutputdataiscontrolledbythemultiplexer  
select controls. A logic HIGH on LEN latches the outputs.  
The Master Reset (MR) overrides all other controls to set  
the Q outputs LOW.  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E256  
Available in 28-pin PLCC package  
PIN NAMES  
BLOCK DIAGRAM  
Pin  
Function  
Parallel Data Inputs  
First-stage Select Inputs  
Second-stage Select Input  
Latch Enable  
D
0a  
0b  
D0x–D2x  
D
Q
0
0
D
D
D
0c  
0d  
SEL1A, SEL1B  
SEL2  
E
N
Q
R
R
R
LEN  
D1a  
D1b  
D1c  
D1d  
MR  
Master Reset  
D
Q
1
1
Q0, Q0–Q2, Q2  
VCCO  
Data Outputs  
E
N
Q
VCC to Output  
D2a  
D2b  
D2c  
D2d  
Q
2
2
D
E
N
Q
SEL1A  
SEL1B  
SEL  
2
LEN  
MR  
Rev.: G  
Amendment: /0  
M9999-032206  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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