Datasheet > SY10E431_06

SY10E431_06

更新时间： 2024-01-05 18:06:57

品牌	Logo	应用领域
麦瑞 - MICREL		触发器
页数	文件大小	规格书
4页	63K
描述
3-BIT DIFFERENTIAL FLIP-FLOP

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SY10E431_06 数据手册

SY10E431

Micrel, Inc.

SY100E431

3-BIT DIFFERENTIAL

FLIP-FLOP

SY10E431

SY100E431

DESCRIPTION

FEATURES

■ Differential D, clock and Q

The SY10/100E431 are 3-bit flip-flops with differential

clock, data input and data output.

■ Extended 100E VEE range of –4.2V to –5.5V

■ VBB output for single-ended use

The asynchronous Set and Reset controls are edge-

triggered rather than level controlled. This allows the user

to rapidly set or reset the flip-flop and then continue

clocking at the next clock edge without the necessity of

de-asserting the set/reset signal (as would be the case

with a level controlled set/reset).

The E431 is also designed with larger internal swings,

an approach intended to minimize the time spent crossing

the threshold region and thus reduces the metastability

susceptibility window.

■ 1100MHz min. toggle frequency

■ Edge-triggered asynchronous set and reset

■ Fully compatible with Motorola MC10E/100E431

■ Available in 28-pin PLCC package

PIN NAMES

BLOCK DIAGRAM

D[0:2], D[0:2]

CLK[0:2], CLK[0:2]

S[0:2]

Function

Differential Data Inputs

Differential Clock Inputs

Edge Triggered Set Inputs

Edge Triggered Reset Inputs

VBB Reference Output

Differential Data Outputs

VCC to Output

CLK

R[0:2]

VBB

Q[0:2], Q[0:2]

VCCO

CLK

(1)

TRUTH TABLE

CLKn

CLK

NOTE:

1. Z = LOW-to-HIGH transition.

VBB

Rev.: E

Amendment: /0

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4

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