5秒后页面跳转
SY10E451 PDF预览

SY10E451

更新时间: 2024-01-12 03:23:19
品牌 Logo 应用领域
麦瑞 - MICREL 时钟
页数 文件大小 规格书
4页 66K
描述
6-BIT REGISTER DIFFERENTIAL DATA CLOCK

SY10E451 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:QCCJ,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.7
其他特性:WITH DIFFERENTIAL CLOCK系列:10E
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.48 mm逻辑集成电路类型:D FLIP-FLOP
湿度敏感等级:2位数:6
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):260
传播延迟(tpd):0.85 ns认证状态:Not Qualified
座面最大高度:4.57 mm表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:11.48 mm最小 fmax:1100 MHz
Base Number Matches:1

SY10E451 数据手册

 浏览型号SY10E451的Datasheet PDF文件第2页浏览型号SY10E451的Datasheet PDF文件第3页浏览型号SY10E451的Datasheet PDF文件第4页 
6-BIT REGISTER  
DIFFERENTIAL DATA CLOCK  
SY10E451  
SY100E451  
FEATURES  
DESCRIPTION  
1100MHz min. toggle frequency  
Extended 100E VEE range of –4.2V to –5.5V  
Differential inputs: data and clock  
VBB output for single-ended use  
Asynchronous Master Reset  
The SY10/100E451 offer six D-type flip-flops with single-  
ended outputs and differential data and clock inputs,  
designed for use in new, high-performance ECL systems.  
The registers are triggered by the rising edge of the CLK  
input.  
A logic HIGH on the Master Reset (MR) input resets all  
outputs to a logic LOW. The VBB output is provided for use  
as a reference voltage for single-ended reception of ECL  
signals to that device only. When used for this purpose, it  
is recommended that VBB is decoupled to VCC via a 0.01µF  
capacitor.  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E451  
Available in 28-pin PLCC package  
PIN CONFIGURATION  
BLOCK DIAGRAM  
D
D
0
0
Q
Q
Q
Q
Q
Q
0
1
2
3
4
5
D
D
D
D
D
D
R
R
R
R
R
R
25  
24 23 22 21 20 19  
D
D
1
1
CLK  
18  
17  
16  
15  
14  
13  
12  
26  
27  
28  
1
Q
Q
5
4
V
BB  
CLK  
VCC  
TOP VIEW  
PLCC  
VEE  
D
D
2
2
Q
3
J28-1  
MR  
NC  
2
VCCO  
3
Q
Q
2
1
D
0
4
D
D
3
3
5
6
7
8
9
10 11  
D
D
4
4
D
D
5
5
PIN NAMES  
Pin  
D0–D5  
D0–D5  
CLK  
Function  
CLK  
CLK  
+ Data Input  
– Data Input  
+ Clock Input  
– Clock Input  
MR  
VBB  
CLK  
MR  
Master Reset Input  
VBB Output  
VBB  
Q0–Q5  
VCCO  
Data Outputs  
VCC to Output  
Rev.: C  
Amendment: /1  
Issue Date: February, 1998  
1

与SY10E451相关器件

型号 品牌 获取价格 描述 数据表
SY10E451_06 MICREL

获取价格

6-BIT REGISTER DIFFERENTIAL DATA CLOCK
SY10E451JC MICROCHIP

获取价格

D Flip-Flop, 10E Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, ECL, PQCC28,
SY10E451JC MICREL

获取价格

6-BIT REGISTER DIFFERENTIAL DATA CLOCK
SY10E451JCTR MICREL

获取价格

6-BIT REGISTER DIFFERENTIAL DATA CLOCK
SY10E451JI MICREL

获取价格

6-BIT REGISTER DIFFERENTIAL DATA CLOCK
SY10E451JI MICROCHIP

获取价格

D Flip-Flop, 10E Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, ECL, PQCC28,
SY10E451JITR MICREL

获取价格

6-BIT REGISTER DIFFERENTIAL DATA CLOCK
SY10E451JY MICREL

获取价格

6-BIT REGISTER DIFFERENTIAL DATA CLOCK
SY10E451JY MICROCHIP

获取价格

10E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC28
SY10E451JYTR MICREL

获取价格

6-BIT REGISTER DIFFERENTIAL DATA CLOCK