SY10E451JC

更新时间： 2024-01-03 20:36:53

品牌	Logo	应用领域
麦瑞 - MICREL		触发器逻辑集成电路时钟
页数	文件大小	规格书
4页	66K
描述
6-BIT REGISTER DIFFERENTIAL DATA CLOCK

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中文翻译

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数据手册

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SY10E451JC 数据手册

6-BIT REGISTER

DIFFERENTIAL DATA CLOCK

SY10E451

SY100E451

FEATURES

DESCRIPTION

■ 1100MHz min. toggle frequency

■ Extended 100E VEE range of –4.2V to –5.5V

■ Differential inputs: data and clock

■ VBB output for single-ended use

■ Asynchronous Master Reset

The SY10/100E451 offer six D-type flip-flops with single-

ended outputs and differential data and clock inputs,

designed for use in new, high-performance ECL systems.

The registers are triggered by the rising edge of the CLK

input.

A logic HIGH on the Master Reset (MR) input resets all

outputs to a logic LOW. The VBB output is provided for use

as a reference voltage for single-ended reception of ECL

signals to that device only. When used for this purpose, it

is recommended that VBB is decoupled to VCC via a 0.01µF

capacitor.

■ Fully compatible with industry standard 10KH,

100K ECL levels

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E451

■ Available in 28-pin PLCC package

PIN CONFIGURATION

BLOCK DIAGRAM

24 23 22 21 20 19

CLK

VCC

TOP VIEW

PLCC

VEE

J28-1

VCCO

10 11

PIN NAMES

D0–D5

CLK

Function

CLK

+ Data Input

– Data Input

+ Clock Input

– Clock Input

VBB

CLK

Master Reset Input

VBB Output

VBB

Q0–Q5

VCCO

Data Outputs

VCC to Output

Rev.: C

Amendment: /1

Issue Date: February, 1998

12 3 4

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SY10E451JI	MICROCHIP	获取价格	D Flip-Flop, 10E Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, ECL, PQCC28,
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SY10E451JY	MICREL	获取价格	6-BIT REGISTER DIFFERENTIAL DATA CLOCK
SY10E451JY	MICROCHIP	获取价格	10E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC28
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SY10E451JY-TR	MICREL	获取价格	D Flip-Flop, 10E Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, ECL, PQCC28,
SY10E452	MICREL	获取价格	5-BIT DIFFERENTIAL REGISTER
SY10E452JC	MICREL	获取价格	5-BIT DIFFERENTIAL REGISTER