SY10E452JCTR

更新时间： 2024-09-30 22:59:23

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
4页	66K
描述
5-BIT DIFFERENTIAL REGISTER

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SY10E452JCTR 数据手册

5-BIT DIFFERENTIAL

SY10E452

SY100E452

DESCRIPTION

FEATURES

■ Differential D, CLK and Q

The SY10/100E452 are 5-bit differential registers with

differential data (inputs and outputs) and clock. The

registers are triggered by a positive transition of the

positive clock (CLK) input. A high on the Master Reset

(MR) asynchronously resets all registers so that the Q

outputs go LOW.

■ Extended 100E VEE range of –4.2V to –5.5V

■ VBB output for single-ended use

■ 1100MHz min. toggle frequency

■ Asynchronous Master Reset

The differential input structures are clamped so that

the inputs of unused registers can be left open without

upsetting the bias network of the devices. The clamping

action will assert the /D and the /CLK sides of the inputs.

Because of the edge-triggered flip-flop nature of the

devices, simultaneously opening both the clock and data

inputs will result in an output which reaches an

unidentified but valid state.

■ Fully compatible with Motorola MC10E/100E452

■ Available in 28-pin PLCC package

The fully differential design of the devices makes them

ideal for very high frequency applications where a

registered data path is necessary.

BLOCK DIAGRAM

PIN CONFIGURATION

24 23 22 21 20 19

CLK

TOP VIEW

PLCC

J28-1

10 11

PIN NAMES

D [0:4], /D [0:4]

Function

Differential Data Inputs

Master Reset Input

Differential Clock Input

VBB Reference Output

Differential Data Outputs

VCC to Output

CLK, /CLK

VBB

CLK

Q [0:4], Q [0:4]

VCCO

Rev.: D

Amendment:/0

Issue Date: May, 1999

12 3 4

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与SY10E452JCTR相关器件

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SY10E452JITR	MICREL	获取价格	5-BIT DIFFERENTIAL REGISTER
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