Datasheet > SY10E336_06

SY10E336_06

更新时间： 2024-02-03 18:49:18

品牌	Logo	应用领域
麦瑞 - MICREL		总线收发器
页数	文件大小	规格书
4页	66K
描述
3-BIT REGISTERED BUS TRANSCEIVER

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数据手册

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SY10E336_06 数据手册

SY10E336

SY100E336

Micrel, Inc.

3-BIT REGISTERED

BUS TRANSCEIVER

SY10E336

SY100E336

FEATURES

DESCRIPTION

■ 25Ω cutoff bus output

The SY10/100E336 offer three bus transceivers with

both transmit and receive registers and are designed for

use in new, high-performance ECL systems. The bus

outputs (BUS0 - BUS2) are designed to drive a 25Ω bus.

The receive outputs (Q0 – Q2) are specified for 50Ω. The

bus outputs feature a normal logic HIGH level (VOH) and a

cutoff LOW level when at a logic LOW. At cutoff, the outputs

go to –2.0V and the output emitter-follower is “off”,

presenting a high impedance to the bus. The bus outputs

have edge slow-down capacitors.

■ Extended 100E VEE range of –4.2V to –5.5V

■ 50Ω receiver output

■ Transmit and receive registers

■ 1500ps max. clock to bus

■ 1000ps max. clock to Q

■ Internal edge slow-down capacitors on bus outputs

■ Additional package ground pins

■ Fully compatible with industry standard 10KH,

The Transmit Enable pins (TEN) determine whether

current data is held in the transmit register or new data is

loaded from the A/B inputs. A logic LOW on both of the bus

enable inputs (BUSEN), when clocked through the register,

disables the bus outputs to –2.0V.

The receiver section clocks bus data into the receive

registers after gating with the Receive Enable (RXEN)

input.

100K ECL levels

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E336

■ Available in 28-pin PLCC package

All registers are clocked by rising edge of CLK1 or CLK2

(or both).

Additional grounding is provided through the ground

pins (GND) which should be connected to 0V. The GND

pins are not electrically connected to the chip.

BLOCK DIAGRAM

25 CUTOFF

PIN NAMES

BUS0

A0–A2

Function

Data Inputs A

25 CUTOFF

BUS1

B0–B2

Data Inputs B

TEN1, 2

RXEN

Transmit Enable Inputs

Receive Enable Input

Bus Enable Inputs

Clock Inputs

25 CUTOFF

BUS2

BUSEN1, 2

CLK1, 2

BUS0–BUS2

Q0–Q2

TEN1

TEN2

25Ω Cutoff Bus Outputs

Receive Data Outputs

VCC to Output

RXEN

BUSEN1

BUSEN2

VCCO

CLK1

CLK2

Rev.: G

Amendment: /0

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4

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