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SY10E416JC PDF预览

SY10E416JC

更新时间: 2024-02-02 13:19:07
品牌 Logo 应用领域
麦瑞 - MICREL 接口集成电路
页数 文件大小 规格书
4页 63K
描述
QUINT DIFFERENTIAL LINE RECEIVER

SY10E416JC 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:LEAD FREE, PLASTIC, LCC-28Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.68输入特性:DIFFERENTIAL
接口集成电路类型:LINE RECEIVER接口标准:GENERAL PURPOSE
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.48 mm湿度敏感等级:2
功能数量:5端子数量:28
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):245认证状态:Not Qualified
最大接收延迟:0.5 ns接收器位数:5
座面最大高度:4.57 mm表面贴装:YES
技术:ECL温度等级:COMMERCIAL EXTENDED
端子面层:MATTE TIN端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:11.48 mm
Base Number Matches:1

SY10E416JC 数据手册

 浏览型号SY10E416JC的Datasheet PDF文件第2页浏览型号SY10E416JC的Datasheet PDF文件第3页浏览型号SY10E416JC的Datasheet PDF文件第4页 
QUINT DIFFERENTIAL  
LINE RECEIVER  
SY10E416  
SY100E416  
DESCRIPTION  
FEATURES  
Differential D and Q  
The SY10/100E416 are 5-bit differential line receiving  
devices. The 2.0GHz of bandwidth provided by the high  
frequency outputs make the devices ideal for buffering  
of very high speed oscillators.  
A VBB pin is available to AC couple an input signal to  
the devices.  
Extended 100E VEE range of –4.2V to –5.5V  
VBB output for single-ended use  
600ps max. propagation delay  
High frequency outputs  
The design incorporates two stages of gain internal to  
the devices, making them an excellent choice for use in  
high bandwidth amplifier applications.  
2 stages of gain  
Internal 75Kinput pull-down resistors  
Fully compatible with Motorola 10E/100E416  
Available in 28-pin PLCC package  
PIN CONFIGURATION  
BLOCK DIAGRAM  
Q0  
Q0  
D0  
D0  
D1  
D0  
Q1  
Q1  
25  
24 23 22 21 20 19  
D
3
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
Q
Q
3
3
D
D
2
2
D2  
D2  
Q2  
Q2  
VCC  
TOP VIEW  
PLCC  
V
EE  
BB  
Q
Q
2
2
J28-1  
V
2
D3  
D3  
Q3  
Q3  
D
0
0
3
VCCO  
D
4
Q
1
5
6
7
8
9
10 11  
D4  
D4  
Q4  
Q4  
VBB  
PIN NAMES  
Pin  
Function  
D[0:4], D[0:4]  
Q[0:4], Q[0:4]  
VCCO  
Differential Data Inputs  
Differential Data Outputs  
VCC to Output  
Rev.: C  
Amendment:/1  
Issue Date: February, 1998  
1

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10E SERIES, TRIPLE POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC28, PLAS