SY10E195JCTR

更新时间： 2024-09-12 22:25:31

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
8页	78K
描述
PROGRAMMABLE DELAY CHIP

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数据手册

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SY10E195JCTR 数据手册

ClockWorks™

SY10E195

PROGRAMMABLE

DELAY CHIP

SY100E195

FEATURES

DESCRIPTION

■ Up to 2ns delay range

The SY10/100E195 are programmable delay chips

(PDCs) designed primarily for clock de-skewing and timing

adjustment. They provide variable delay of a differential

ECL input transition.

The delay section consists of a chain of gates

organized as shown in the logic diagram. The first two

delay elements feature gates that have been modified to

have delays 1.25 and 1.5 times the basic gate delay of

approximately 80ps. These two elements provide the

■ Extended 100E VEE range of –4.2V to –5.5V

■ ≈20ps/digital step resolution

■ >1GHz bandwidth

■ On-chip cascade circuitry

■ 75KkΩ input pulldown resistor

■ Fully compatible with Motorola MC10E/100E195

■ Available in 28-pin PLCC package

E195 with

digitally-selectable resolution of

approximately 20ps. The required device delay is selected

by the seven address inputs D[0:6], which are latched

on-chip by a high signal on the latch enable (LEN) control.

If the LEN signal is either LOW or left floating, then the

latch is transparent.

Because the delay programmability of the E195 is

achieved by purely differential ECL gate delays, the

device will operate at frequencies of >1GHz, while

maintaining over 600mV of output swing.

PIN CONFIGURATION

The E195 thus offers very fine resolution, at very high

frequencies, selectable entirely from a digital input,

allowing for very accurate system clock timing.

An eighth latched input, D7, is provided for cascading

multiple PDCs for increased programmable range. The

cascade logic allows full control of multiple PDCs, at the

expense of only a single added line to the data bus for

each additional PDC, without the need for any external

gating.

24 23 22 21 20 19

VCC

VCCO

LEN

VEE

TOP VIEW

PLCC

J28-1

VBB

VCCO

10 11

PIN NAMES

Function

Signal Input

IN/IN

Input Enable

D[0:7]

Mux Select Inputs

Signal Output

Q/Q

LEN

Latch Enable

SET MIN

SET MAX

CASCADE

Minimum Delay Set

Maximum Delay Set

Cascade Signal

Rev.: E

Amendment:/0

Issue Date: October, 1998

12 3 4 5 6 7 8

中文翻译

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