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SY10E196JC

更新时间： 2024-09-12 22:25:31

品牌	Logo	应用领域
麦瑞 - MICREL		输入元件
页数	文件大小	规格书
9页	82K
描述
PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT

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SY10E196JC 数据手册

ClockWorks™

SY10E196

PROGRAMMABLE DELAY

CHIP WITH ANALOG INPUT

SY100E196

DESCRIPTION

FEATURES

■ Up to 2ns delay range

The SY10/100E196 are programmable delay chips

(PDCs) designed primarily for very accurate differential

ECL input edge placement applications.

■ Extended 100E VEE range of –4.2V to –5.5V

■ ≈20ps digital step resolution

■ Linear input for tighter resolution

■ >1GHz bandwidth

The delay section consists of a chain of gates and a

linear ramp delay adjustment organized as shown in the

logic diagram. The first two delay elements feature gates

that have been modified to have delays 1.25 and 1.5

times the basic gate delay of approximately 80ps. These

two elements provide the E196 with a digitally-selectable

resolution of approximately 20ps. The required device

delay is selected by the seven address inputs D[0:6],

which are latched on-chip by a high signal on the latch

enable (LEN) control. If the LEN signal is either LOW or

left floating, then the latch is transparent.

■ On-chip cascade circuitry

■ 75KkΩ input pulldown resistor

■ Fully compatible with Motorola MC10E/100E196

■ Available in 28-pin PLCC package

The FTUNE input takes an analog coltage and applies

it to an internal linear ramp for reducing the 20s resolution

still further. The FTUNE input is what differentiates the

E196 from the E195.

PIN CONFIGURATION

An eighth latched input, D7, is provided for cascading

multiple PDCs for increased programmable range. The

cascade logic allows full control of multiple PDCs, at the

expense of only a single added line to the data bus for

each additional PDC, without the need for any external

gating.

24 23 22 21 20 19

FTUNE

LEN

TOP VIEW

PLCC

CCO

J28-1

PIN NAMES

CCO

Function

Signal Input

10 11

IN/IN

Input Enable

D[0:7]

Mux Select Inputs

Signal Output

Q/Q

LEN

Latch Enable

SET MIN

SET MAX

CASCADE

FTUNE

VCCO

Minimum Delay Set

Maximum Delay Set

Cascade Signal

Linear Voltage Input

VCC to Output

Rev.: E

Amendment:/0

Issue Date: October, 1998

12 3 4 5 6 7...9

中文翻译

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