SY100EL31

更新时间： 2024-09-15 05:16:11

品牌	Logo	应用领域
麦瑞 - MICREL		触发器
页数	文件大小	规格书
4页	50K
描述
D FLIP-FLOP WITH SET AND RESET

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

SY100EL31 数据手册

SY10EL31

Micrel, Inc.

SY100EL31

D FLIP-FLOP

SY10EL31

SY100EL31

WITH SET AND RESET

FEATURES

DESCRIPTION

■ 475ps propagation delay

The SY10/100EL31 are D flip-flops with set and reset.

The devices are functionally equivalent to the E131

devices, with higher performance capabilities. With

propagation delays and output transition times

significantly faster than the E131, the EL31 is ideally

suited for those applications which require the ultimate

in AC performance.

■ 2.8GHz toggle frequency

■ Internal 75KΩ input pull-down resistors

■ Available in 8-pin SOIC package

Both the set and reset inputs are asynchronous, level

triggered signals. Data enters the master portion of the

flip-flop when the clock is LOW and is transferred to the

slave, and thus the outputs, upon a positive transition of

the clock.

PIN NAMES

Function

Data Inputs

Data Outputs

Set

Reset

CLK

Clock Input

(1)

TRUTH TABLE

CLK

Undef

NOTE:

1. Z = LOW-to-HIGH transition.

Rev.: G

Amendment:/0

M9999-120705

hbwhelp@micrel.com or (408) 955-1690

Issue Date: December2005

12 3 4

中文翻译

下载PDF

与SY100EL31相关器件

型号	品牌	获取价格	描述	数据表
SY100EL31ZC	MICREL	获取价格	D FLIP-FLOP WITH SET AND RESET
SY100EL31ZC	MICROCHIP	获取价格	D Flip-Flop, 100EL Series, 1-Func, Positive Edge Triggered, 1-Bit, Complementary Output, E
SY100EL31ZCTR	MICREL	获取价格	D FLIP-FLOP WITH SET AND RESET
SY100EL31ZG	MICREL	获取价格	D FLIP-FLOP WITH SET AND RESET
SY100EL31ZG	MICROCHIP	获取价格	100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
SY100EL31ZGTR	MICREL	获取价格	D FLIP-FLOP WITH SET AND RESET
SY100EL31ZI	MICROCHIP	获取价格	D Flip-Flop, 100EL Series, 1-Func, Positive Edge Triggered, 1-Bit, Complementary Output, E
SY100EL31ZI	MICREL	获取价格	D FLIP-FLOP WITH SET AND RESET
SY100EL31ZITR	MICREL	获取价格	D FLIP-FLOP WITH SET AND RESET
SY100EL32V	MICROCHIP	获取价格	The SY100EL32V is an integrated divide by 2 divider. The differential clock inputs and the