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SY100EL32VZCTR PDF预览

SY100EL32VZCTR

更新时间: 2024-02-08 17:17:54
品牌 Logo 应用领域
麦瑞 - MICREL 预分频器多谐振动器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
4页 52K
描述
5V/3.3V ± 2 DIVIDER

SY100EL32VZCTR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.7
系列:100ELJESD-30 代码:R-PDSO-G8
JESD-609代码:e0逻辑集成电路类型:MONOSTABLE MULTIVIBRATOR
最大频率@ Nom-Sup:2600000000 Hz数据/时钟输入次数:1
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:-4.5 V最大电源电流(ICC):35 mA
认证状态:Not Qualified子类别:Prescaler/Multivibrators
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL最小 fmax:2600 MHz

SY100EL32VZCTR 数据手册

 浏览型号SY100EL32VZCTR的Datasheet PDF文件第2页浏览型号SY100EL32VZCTR的Datasheet PDF文件第3页浏览型号SY100EL32VZCTR的Datasheet PDF文件第4页 
ClockWorks™  
SY10EL32V  
SY100EL32V  
5V/3.3V ÷ 2 DIVIDER  
FEATURES  
DESCRIPTION  
3.3V and 5V power supply options  
510ps propagation delay  
The SY10/100EL32V are integrated ÷2 dividers. The  
differential clock inputs and the VBB allow a differential,  
single-ended or AC-coupled interface to the device. If  
used, the VBB output should be bypassed to ground with  
a 0.01µF capacitor. Also note that the VBB is designed to  
be used as an input bias on the EL32V only; the VBB  
output has limited current sink and source capability.  
The reset pin is asynchronous and is asserted on the  
rising edge. Upon power-on, the internal flip-flop will attain  
a random state; the reset allows for the synchronization  
of multiple EL32Vs in a system.  
3.0GHz toggle frequency  
High bandwidth output transistions  
Internal 75Kinput pull-down resistors  
Available in 8-pin SOIC package  
PIN NAMES  
PIN CONFIGURATION/BLOCK DIAGRAM  
Pin  
CLK  
Function  
Clock Inputs  
Reset  
CLK  
VCC  
Q
1
2
8
7
Reset  
VBB  
Q
Asynchronous Reset  
Reference Voltage Output  
Data Outputs  
R
÷ 2  
CLK  
VBB  
3
4
Q
6
5
VEE  
SOIC  
TOP VIEW  
Rev.: C  
Amendment:/0  
Issue Date: August, 1998  
1

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