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SY100EL31ZC PDF预览

SY100EL31ZC

更新时间: 2024-11-23 22:13:19
品牌 Logo 应用领域
麦瑞 - MICREL 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
4页 51K
描述
D FLIP-FLOP WITH SET AND RESET

SY100EL31ZC 数据手册

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D FLIP-FLOP  
WITH SET AND RESET  
SY10EL31  
SY100EL31  
FEATURES  
DESCRIPTION  
475ps propagation delay  
The SY10/100EL31 are D flip-flops with set and reset.  
The devices are functionally equivalent to the E131  
devices, with higher performance capabilities. With  
propagation delays and output transition times  
significantly faster than the E131, the EL31 is ideally  
suited for those applications which require the ultimate  
in AC performance.  
2.8GHz toggle frequency  
Internal 75Kinput pull-down resistors  
Available in 8-pin SOIC package  
Both the set and reset inputs are asynchronous, level  
triggered signals. Data enters the master portion of the  
flip-flop when the clock is LOW and is transferred to the  
slave, and thus the outputs, upon a positive transition of  
the clock.  
PIN NAMES  
PIN CONFIGURATION/BLOCK DIAGRAM  
Pin  
D
Function  
Data Inputs  
Q
Data Outputs  
Set  
S
D
VCC  
1
2
8
7
S
S
Q
Q
D
R
Reset  
Flip-Flop  
CLK  
Clock Input  
CLK  
R
3
4
6
5
R
VEE  
(1)  
TRUTH TABLE  
SOIC  
TOP VIEW  
D
L
S
L
R
L
CLK  
Z
Q
L
H
H
X
X
X
L
L
Z
H
L
L
X
H
H
H
X
L
H
X
Undef  
NOTE:  
1. Z = LOW-to-HIGH transition.  
Rev.: E  
Amendment:/0  
Issue Date: August, 1998  
1

SY100EL31ZC 替代型号

型号 品牌 替代类型 描述 数据表
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100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
MC100EL31DG ONSEMI

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5 V ECL D Flip-Flop With Set and Reset

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