SY100EL14V

更新时间： 2024-11-23 22:40:43

品牌	Logo	应用领域
麦瑞 - MICREL		时钟
页数	文件大小	规格书
4页	70K
描述
5V/3.3V 1:5 CLOCK DISTRIBUTION

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中文翻译

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数据手册

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SY100EL14V 数据手册

5V/3.3V 1:5 CLOCK

DISTRIBUTION

ClockWorks™

SY100EL14V

FEATURES

DESCRIPTION

The SY100EL14V is a low skew 1:5 clock distribution

chip designed explicitly for low skew clock distribution

applications. The device can be driven by either a

differential or single-ended ECL or, if positive power

supplies are used, PECL input signal. The EL14V is

suitable for operation in systems operating from 3.3V to

5.0V supplies. If a single-ended input is to be used the

VBB output should be connected to the CLK input and

bypassed to ground via a 0.01µF capacitor. The VBB

output is designed to act as the switching reference for

the input of the EL14V under single-ended input

conditions, as a result this pin can only source/sink up to

0.5mA of current.

■ 3.3V and 5V power supply options

■ Typical 30ps output-to-output skew

■ Max. 50ps output-to-output skew

■ Synchronous enable/disable

■ Multiplexed clock input

■ 75KΩ internal input pull-down resistors

■ Available in 20-pin SOIC package

The EL14V features a multiplexed clock input to allow

for the distribution of a lower speed scan or test clock

along with the high speed system clock. When LOW (or

left open and pulled LOW by the input pull-down resistor)

the SEL pin will select the differential clock input.

The common enable (EN) is synchronous so that the

outputs will only be enabled/disabled when they are

already in the LOW state. This avoids any chance of

generating a runt clock pulse when the device is enabled/

disabled as can happen with an asynchronous control.

The internal flip flop is clocked on the falling edge of the

input clock, therefore all associated specification limits

are referenced to the negative edge of the clock input.

When both differential inputs are left open, CLK input

will pull down to VEE and CLK input will bias around

VCC/2.

PIN CONFIGURATION/BLOCK DIAGRAM

VCC EN VCC NC SCLK CLK CLK VBB SEL

VEE

20 19 18 17 16 15 14 13 12 11

Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4

SOIC

TOP VIEW

PIN NAMES

TRUTH TABLE

CLK

SCLK

Function

Differential Clock Inputs

Scan Clock Input

CLK

SCLK

SEL

Synchronous Enable

Clock Select Input

SEL

VBB

Reference Output

Q0-4

Differential Clock Outputs

* On next negative transition of CLK or SCLK

Rev.: A

Amendment:/0

Issue Date: October 1999

12 3 4

中文翻译

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与SY100EL14V相关器件

型号	品牌	获取价格	描述	数据表
SY100EL14V_06	MICREL	获取价格	5V/3.3V 1:5 CLOCK DISTRIBUTION
SY100EL14VZC	MICREL	获取价格	5V/3.3V 1:5 CLOCK DISTRIBUTION
SY100EL14VZCTR	MICREL	获取价格	5V/3.3V 1:5 CLOCK DISTRIBUTION
SY100EL14VZG	MICREL	获取价格	5V/3.3V 1:5 CLOCK DISTRIBUTION
SY100EL14VZGTR	MICREL	获取价格	5V/3.3V 1:5 CLOCK DISTRIBUTION
SY100EL14VZI	MICREL	获取价格	5V/3.3V 1:5 CLOCK DISTRIBUTION
SY100EL14VZITR	MICREL	获取价格	5V/3.3V 1:5 CLOCK DISTRIBUTION
SY100EL14VZY	MICROCHIP	获取价格	100EL SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
SY100EL14VZYTR	MICREL	获取价格	暂无描述
SY100EL14VZYTR	MICROCHIP	获取价格	100EL SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20, 0.300

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