Datasheet > SY100EL14VZY-TR

SY100EL14VZY-TR

更新时间： 2024-11-21 04:04:35

品牌	Logo	应用领域
美国微芯 - MICROCHIP		驱动光电二极管输出元件
页数	文件大小	规格书
4页	56K
描述
100EL SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

SY100EL14VZY-TR 数据手册

5V/3.3V 1:5 CLOCK

DISTRIBUTION

Precision Edge™

SY100EL14V

FEATURES

■ 3.3V and 5V power supply options

■ Typical 30ps output-to-output skew

■ Max. 50ps output-to-output skew

■ Synchronous enable/disable

Precision Edge™

DESCRIPTION

■ Multiplexed clock input

The SY100EL14V is a low skew 1:5 clock distribution

chip designed explicitly for low skew clock distribution

applications. The device can be driven by either a

differential or single-ended ECL or, if positive power

supplies are used, PECL input signal. The EL14V is

suitable for operation in systems operating from 3.3V to

5.0V supplies. If a single-ended input is to be used the

VBB output should be connected to the CLK input and

bypassed to ground via a 0.01µF capacitor. The VBB

output is designed to act as the switching reference for

the input of the EL14V under single-ended input

conditions, as a result this pin can only source/sink up to

0.5mA of current.

■ 75KΩ internal input pull-down resistors

■ Available in 20-pin SOIC package

PIN CONFIGURATION/BLOCK DIAGRAM

VCC EN VCC NC SCLK CLK CLK VBB SEL

VEE

20 19 18 17 16 15 14 13 12 11

The EL14V features a multiplexed clock input to allow

for the distribution of a lower speed scan or test clock

along with the high speed system clock. When LOW (or

left open and pulled LOW by the input pull-down resistor)

the SEL pin will select the differential clock input.

The common enable (EN) is synchronous so that the

outputs will only be enabled/disabled when they are

already in the LOW state. This avoids any chance of

generating a runt clock pulse when the device is enabled/

disabled as can happen with an asynchronous control.

The internal flip flop is clocked on the falling edge of the

input clock, therefore all associated specification limits

are referenced to the negative edge of the clock input.

When both differential inputs are left open, CLK input

will pull down to VEE and CLK input will bias around

VCC/2.

Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4

SOIC

TOP VIEW

PIN NAMES

TRUTH TABLE

CLK

SCLK

Function

Differential Clock Inputs

Scan Clock Input

CLK

SCLK

SEL

Synchronous Enable

Clock Select Input

SEL

VBB

Reference Output

Q0-4

Differential Clock Outputs

* On next negative transition of CLK or SCLK

Precision Edge is a trademark of Micrel, Inc.

Rev.: C

Amendment:/0

IssueDate: September2004

12 3 4

中文翻译

下载PDF

与SY100EL14VZY-TR相关器件

型号	品牌	获取价格	描述	数据表
SY100EL15	MICREL	获取价格	1:4 CLOCK DISTRIBUTION
SY100EL15L	MICREL	获取价格	3.3V 1:4 CLOCK DISTRIBUTION
SY100EL15L	MICROCHIP	获取价格	The SY100EL15L is a low skew 1:4 clock distribution IC designed explicitly for low skew cl
SY100EL15L_06	MICREL	获取价格	3.3V 1:4 CLOCK DISTRIBUTION
SY100EL15LZC	MICREL	获取价格	3.3V 1:4 CLOCK DISTRIBUTION
SY100EL15LZCTR	MICREL	获取价格	3.3V 1:4 CLOCK DISTRIBUTION
SY100EL15LZG	MICREL	获取价格	3.3V 1:4 CLOCK DISTRIBUTION
SY100EL15LZG	MICROCHIP	获取价格	100EL SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SY100EL15LZGTR	MICREL	获取价格	3.3V 1:4 CLOCK DISTRIBUTION
SY100EL15LZG-TR	MICROCHIP	获取价格	100EL SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16

与SY100EL14VZY-TR相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

25
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

17
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

49
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

46

产品中心

服务支持

精选活动

关于我们

帮助中心

SY100EL14VZY-TR

SY100EL14VZY-TR 数据手册

与SY100EL14VZY-TR相关器件

与SY100EL14VZY-TR相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SY100EL14VZY-TR

SY100EL14VZY-TR 数据手册

与SY100EL14VZY-TR相关器件

与SY100EL14VZY-TR相关文章

您还可以找

您在本页遇到什么问题？