Datasheet > SY100EL15L

SY100EL15L

更新时间： 2024-11-25 14:55:15

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
4页	58K
描述
The SY100EL15L is a low skew 1:4 clock distribution IC designed explicitly for low skew clock dist

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SY100EL15L 数据手册

ClockWorks™

Micrel

SY100EL15L

3.3V 1:4 CLOCK

DISTRIBUTION

ClockWorks™

SY100EL15L

Synergy™ High-Speed Products

FEATURES

DESCRIPTION

The SY100EL15L is a low skew 1:4 clock distribution

IC designed explicitly for low skew clock distribution

applications. The device can be driven by either a

differential or single-ended ECL or, if positive power

supplies are used, PECL input signal. If a single-ended

input is to be used the VBB output should be connected

to the CLK input and bypassed to ground via a 0.01µF

capacitor. The VBB output is designed to act as the

switching reference for the input of the EL15 under single-

ended input conditions. As a result, this pin can only

source/sink up to 0.5mA of current.

■ 3.3V power supply

■ 50ps output-to-output skew

■ Low power

■ Synchronous enable/disable

■ Multiplexed clock input

■ 75KΩ internal input pull-down resistors

■ ESD protection of 2000V

■ Available in 16-pin SOIC package

The EL15 features a multiplexed clock input to allow

for the distribution of a lower speed scan or test clock

along with the high speed system clock. When LOW (or

left open and pulled LOW by the input pull-down resistor)

the SEL pin will select the differential clock input.

The common enable (EN) is synchronous so that the

outputs will only be enabled/disabled when they are

already in the LOW state. This avoids any chance of

generating a runt clock pulse when the device is enabled/

disabled as can happen with an asynchronous control.

The internal flip flop is clocked on the falling edge of the

input clock, therefore all associated specification limits

are referenced to the negative edge of the clock input.

When both differential inputs are left open, CLK input

will pull down to VEE and CLK input will bias around

VCC/2.

PIN CONFIGURATION/BLOCK DIAGRAM

CLK CLK

13 12

VBB

CC EN SCLK

VEE

SEL

16 15 14

SOIC

TOP VIEW

PIN NAMES

TRUTH TABLE

CLK

SCLK

Function

CLK

SCLK

SEL

Differential Clock Inputs

Synchronous Clock Input

Synchronous Enable

Clock Select Input

SEL

VBB

Reference Output

Q0-3

Differential Clock Outputs

* On next negative transition of CLK or SCLK

Rev.: A

Amendment:/0

Issue Date: December 1999

12 3 4

中文翻译

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与SY100EL15L相关器件

型号	品牌	获取价格	描述	数据表
SY100EL15L_06	MICREL	获取价格	3.3V 1:4 CLOCK DISTRIBUTION
SY100EL15LZC	MICREL	获取价格	3.3V 1:4 CLOCK DISTRIBUTION
SY100EL15LZCTR	MICREL	获取价格	3.3V 1:4 CLOCK DISTRIBUTION
SY100EL15LZG	MICREL	获取价格	3.3V 1:4 CLOCK DISTRIBUTION
SY100EL15LZG	MICROCHIP	获取价格	100EL SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SY100EL15LZGTR	MICREL	获取价格	3.3V 1:4 CLOCK DISTRIBUTION
SY100EL15LZG-TR	MICROCHIP	获取价格	100EL SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SY100EL15LZI	MICREL	获取价格	3.3V 1:4 CLOCK DISTRIBUTION
SY100EL15LZI	MICROCHIP	获取价格	Low Skew Clock Driver, 100EL Series, 4 True Output(s), 0 Inverted Output(s), ECL, PDSO16,
SY100EL15LZITR	MICREL	获取价格	3.3V 1:4 CLOCK DISTRIBUTION

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