SY100EL15LZG

更新时间： 2024-11-20 07:17:11

品牌	Logo	应用领域
麦瑞 - MICREL		逻辑集成电路光电二极管驱动时钟
页数	文件大小	规格书
5页	60K
描述
3.3V 1:4 CLOCK DISTRIBUTION

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

SY100EL15LZG 数据手册

Precision Edge^®

Micrel, Inc.

SY100EL®15L

3.3V 1:4 CLOCK

DISTRIBUTION

Precision Edge

SY100EL15L

FEATURES

■ 3.3V power supply

Precision Edge

■ 50ps output-to-output skew

■ Low power

DESCRIPTION

■ Synchronous enable/disable

■ Multiplexed clock input

The SY100EL15L is a low skew 1:4 clock distribution

IC designed explicitly for low skew clock distribution

applications. The device can be driven by either a

differential or single-ended ECL or, if positive power

supplies are used, PECL input signal. If a single-ended

input is to be used the VBB output should be connected

to the CLK input and bypassed to ground via a 0.01µF

capacitor. The VBB output is designed to act as the

switching reference for the input of the EL15 under single-

ended input conditions. As a result, this pin can only

source/sink up to 0.5mA of current.

■ 75KΩ internal input pull-down resistors

■ Available in 16-pin SOIC package

The EL15 features a multiplexed clock input to allow

for the distribution of a lower speed scan or test clock

along with the high speed system clock. When LOW (or

left open and pulled LOW by the input pull-down resistor)

the SEL pin will select the differential clock input.

The common enable (EN) is synchronous so that the

outputs will only be enabled/disabled when they are

already in the LOW state. This avoids any chance of

generating a runt clock pulse when the device is enabled/

disabled as can happen with an asynchronous control.

The internal flip flop is clocked on the falling edge of the

input clock, therefore all associated specification limits

are referenced to the negative edge of the clock input.

When both differential inputs are left open, CLK input

will pull down to VEE and CLK input will bias around

VCC/2.

PIN NAMES

TRUTH TABLE

CLK

SCLK

Function

Differential Clock Inputs

Synchronous Clock Input

Synchronous Enable

Clock Select Input

CLK

SCLK

SEL

VBB

Reference Output

Q0-3

Differential Clock Outputs

* On next negative transition of CLK or SCLK

Precision Edge is a registered trademark of Micrel, Inc.

Rev.: D

Amendment:/0

M9999-031306

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4 5

中文翻译

下载PDF

与SY100EL15LZG相关器件

型号	品牌	获取价格	描述	数据表
SY100EL15LZGTR	MICREL	获取价格	3.3V 1:4 CLOCK DISTRIBUTION
SY100EL15LZG-TR	MICROCHIP	获取价格	100EL SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SY100EL15LZI	MICREL	获取价格	3.3V 1:4 CLOCK DISTRIBUTION
SY100EL15LZI	MICROCHIP	获取价格	Low Skew Clock Driver, 100EL Series, 4 True Output(s), 0 Inverted Output(s), ECL, PDSO16,
SY100EL15LZITR	MICREL	获取价格	3.3V 1:4 CLOCK DISTRIBUTION
SY100EL15ZC	MICREL	获取价格	1:4 CLOCK DISTRIBUTION
SY100EL15ZCTR	MICREL	获取价格	1:4 CLOCK DISTRIBUTION
SY100EL15ZG	MICREL	获取价格	1:4 CLOCK DISTRIBUTION
SY100EL15ZGTR	MICREL	获取价格	1:4 CLOCK DISTRIBUTION
SY100EL15ZI	MICREL	获取价格	1:4 CLOCK DISTRIBUTION

与SY100EL15LZG相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

25
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

17
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

49
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

46

产品中心

服务支持

精选活动

关于我们

帮助中心

SY100EL15LZG

SY100EL15LZG 数据手册

与SY100EL15LZG相关器件

与SY100EL15LZG相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SY100EL15LZG

SY100EL15LZG 数据手册

与SY100EL15LZG相关器件

与SY100EL15LZG相关文章

您还可以找

您在本页遇到什么问题？