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SY100EL14VZYTR

更新时间: 2024-01-07 10:51:41
品牌 Logo 应用领域
美国微芯 - MICROCHIP 驱动光电二极管输出元件
页数 文件大小 规格书
4页 56K
描述
100EL SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20, 0.300 INCH, LEAD FREE, SOIC-20

SY100EL14VZYTR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SOIC
包装说明:SOP,针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.22系列:100EL
输入调节:DIFFERENTIAL MUXJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:12.83 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:2
功能数量:1反相输出次数:
端子数量:20实输出次数:5
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260传播延迟(tpd):0.83 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.05 ns
座面最大高度:2.65 mm表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:7.52 mm
Base Number Matches:1

SY100EL14VZYTR 数据手册

 浏览型号SY100EL14VZYTR的Datasheet PDF文件第2页浏览型号SY100EL14VZYTR的Datasheet PDF文件第3页浏览型号SY100EL14VZYTR的Datasheet PDF文件第4页 
5V/3.3V 1:5 CLOCK  
DISTRIBUTION  
Precision Edge™  
SY100EL14V  
FEATURES  
3.3V and 5V power supply options  
Typical 30ps output-to-output skew  
Max. 50ps output-to-output skew  
Synchronous enable/disable  
Precision Edge™  
DESCRIPTION  
Multiplexed clock input  
The SY100EL14V is a low skew 1:5 clock distribution  
chip designed explicitly for low skew clock distribution  
applications. The device can be driven by either a  
differential or single-ended ECL or, if positive power  
supplies are used, PECL input signal. The EL14V is  
suitable for operation in systems operating from 3.3V to  
5.0V supplies. If a single-ended input is to be used the  
VBB output should be connected to the CLK input and  
bypassed to ground via a 0.01µF capacitor. The VBB  
output is designed to act as the switching reference for  
the input of the EL14V under single-ended input  
conditions, as a result this pin can only source/sink up to  
0.5mA of current.  
75Kinternal input pull-down resistors  
Available in 20-pin SOIC package  
PIN CONFIGURATION/BLOCK DIAGRAM  
VCC EN VCC NC SCLK CLK CLK VBB SEL  
VEE  
20 19 18 17 16 15 14 13 12 11  
D
Q
1
0
The EL14V features a multiplexed clock input to allow  
for the distribution of a lower speed scan or test clock  
along with the high speed system clock. When LOW (or  
left open and pulled LOW by the input pull-down resistor)  
the SEL pin will select the differential clock input.  
The common enable (EN) is synchronous so that the  
outputs will only be enabled/disabled when they are  
already in the LOW state. This avoids any chance of  
generating a runt clock pulse when the device is enabled/  
disabled as can happen with an asynchronous control.  
The internal flip flop is clocked on the falling edge of the  
input clock, therefore all associated specification limits  
are referenced to the negative edge of the clock input.  
When both differential inputs are left open, CLK input  
will pull down to VEE and CLK input will bias around  
VCC/2.  
1
2
3
4
5
6
7
8
9
10  
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4  
SOIC  
TOP VIEW  
PIN NAMES  
TRUTH TABLE  
Pin  
CLK  
SCLK  
EN  
Function  
Differential Clock Inputs  
Scan Clock Input  
CLK  
L
SCLK  
SEL  
L
EN  
L
Q
L
X
X
L
H
L
L
H
L
Synchronous Enable  
Clock Select Input  
X
H
L
SEL  
VBB  
X
H
X
H
L
H
L*  
Reference Output  
X
X
H
Q0-4  
Differential Clock Outputs  
* On next negative transition of CLK or SCLK  
Precision Edge is a trademark of Micrel, Inc.  
Rev.: C  
Amendment:/0  
IssueDate: September2004  
1

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