ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢀ
ꢁ
ꢌ
ꢃ
ꢍ ꢎꢍ ꢏꢅ ꢐꢑꢆ ꢒ ꢓꢐꢔꢕ ꢓꢖꢄ ꢗ ꢑꢓꢀ ꢑ ꢓꢘ ꢘꢗ ꢕ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢊ
ꢀ
ꢀ
ꢙ
ꢚ
ꢆ
ꢇ
ꢍ
ꢏ
ꢀ
ꢆ
ꢐ
ꢆ
ꢗ
ꢛ
ꢓ
ꢆ
ꢖ
ꢓ
ꢆ
SCBS746B − JULY 2000 - REVISED OCTOBER 2003
SN54LVTH126 . . . J OR W PACKAGE
SN74LVTH126 . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
)
CC
Support Unregulated Battery Operation
Down to 2.7 V
1OE
1A
1Y
2OE
2A
2Y
V
CC
4OE
1
2
3
4
5
6
7
14
13
12
11
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
4A
4Y
A
I
and Power-Up 3-State Support Hot
off
Insertion
10 3OE
3A
3Y
9
8
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
GND
D
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
SN54LVTH126 . . . FK PACKAGE
(TOP VIEW)
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
3
2
1
20 19
18 4A
− 1000-V Charged-Device Model (C101)
1Y
NC
4
5
6
7
8
17
16
15
14
NC
4Y
description/ordering information
2OE
NC
NC
3OE
These bus buffers are designed specifically for
2A
low-voltage (3.3-V) V
operation, but with the
CC
9 10 11 12 13
capability to provide a TTL interface to a 5-V
system environment.
The ’LVTH126 devices feature independent line
drivers with 3-state outputs. Each output is in the
high-impedance state when the associated
output-enable (OE) input is low.
NC − No internal connection
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74LVTH126D
SOIC − D
LVTH126
Tape and reel
Tape and reel
Tape and reel
Tube
SN74LVTH126DR
SN74LVTH126NSR
SN74LVTH126DBR
SN74LVTH126PW
SN74LVTH126PWR
SN74LVTH126DGVR
SNJ54LVTH126J
SNJ54LVTH126W
SNJ54LVTH126FK
SOP − NS
LVTH126
LXH126
SSOP − DB
−40°C to 85°C
−55°C to 125°C
TSSOP − PW
LXH126
Tape and reel
Tape and reel
Tube
TVSOP − DGV
CDIP − J
LXH126
SNJ54LVTH126J
SNJ54LVTH126W
SNJ54LVTH126FK
CFP − W
Tube
LCCC − FK
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
ꢓ ꢁ ꢄꢗꢀꢀ ꢛ ꢆꢇ ꢗꢕꢙ ꢚꢀ ꢗ ꢁ ꢛꢆꢗꢔ ꢜꢝ ꢞꢟ ꢠꢡꢢ ꢣꢤꢥ ꢦꢜ ꢢꢡ ꢦꢜꢧ ꢞꢦꢟ ꢖꢕ ꢛ ꢔ ꢓ ꢨꢆ ꢚꢛ ꢁ
ꢜ
ꢔ
ꢐ
ꢆ
ꢐ
ꢞ
ꢦ
ꢩ
ꢡ
ꢪ
ꢤ
ꢧ
ꢜ
ꢞ
ꢡ
ꢦ
ꢢ
ꢣ
ꢪ
ꢪ
ꢥ
ꢦ
ꢜ
ꢧ
ꢟ
ꢡ
ꢩ
ꢫ
ꢣ
ꢬ
ꢭ
ꢞ
ꢢ
ꢧ
ꢜ
ꢞ
ꢡ
ꢦ
ꢠ
ꢧ
ꢥ
ꢎ
ꢖ
ꢪ
ꢡ
ꢠ
ꢣ
ꢢ
ꢜ
ꢟ
ꢢ
ꢡ
ꢦ
ꢩ
ꢡ
ꢪ
ꢤ
ꢜ
ꢡ
ꢟ
ꢫ
ꢥ
ꢢ
ꢞ
ꢩ
ꢞ
ꢢ
ꢧ
ꢜ
ꢞ
ꢡ
ꢦ
ꢟ
ꢫ
ꢥ
ꢪ
ꢜ
ꢝ
ꢥ
ꢜ
ꢥ
ꢪ
ꢤ
ꢟ
ꢡ
ꢩ
ꢆ
ꢥ
ꢮ
ꢧ
ꢟ
ꢚ
ꢦ
ꢟ
ꢜ
ꢪ
ꢣ
ꢤ
ꢥ
ꢦ
ꢜ
ꢟ
ꢟ
ꢜ
ꢧ
ꢦ
ꢠ
ꢧ
ꢪ
ꢠ
ꢯ
ꢧ
ꢪ
ꢪ
ꢧ
ꢦ
ꢜ
ꢰ
ꢎ
ꢖ
ꢪ
ꢡ
ꢠ
ꢣ
ꢢ
ꢜ
ꢞ
ꢡ
ꢦ
ꢫꢧ ꢪ ꢧ ꢤ ꢥ ꢜ ꢥ ꢪ ꢟ ꢎ
ꢫ
ꢪ
ꢡ
ꢢ
ꢥ
ꢟ
ꢟ
ꢞ
ꢦ
ꢱ
ꢠ
ꢡ
ꢥ
ꢟ
ꢦ
ꢡ
ꢜ
ꢦ
ꢥ
ꢢ
ꢥ
ꢟ
ꢟ
ꢧ
ꢪ
ꢞ
ꢭ
ꢰ
ꢞ
ꢦ
ꢢ
ꢭ
ꢣ
ꢠ
ꢥ
ꢜ
ꢥ
ꢟ
ꢜ
ꢞ
ꢦ
ꢱ
ꢡ
ꢩ
ꢧ
ꢭ
ꢭ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265