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SNJ54LVTH2245J

更新时间： 2024-11-23 05:16:51
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
17页 591K
描述
3.3-V ABT OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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中文翻译

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SNJ54LVTH2245J 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP20,.3针数：20
Reach Compliance Code：unknown风险等级：5.84
其他特性：WITH DIRECTION CONTROL控制类型：COMMON CONTROL
计数方向：BIDIRECTIONAL系列：LVT
JESD-30 代码：R-GDIP-T20长度：24.195 mm
逻辑集成电路类型：BUS TRANSCEIVER最大I（ol）：0.048 A
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP20,.3封装形状：RECTANGULAR
封装形式：IN-LINE包装方法：TUBE
电源：3.3 VProp。Delay @ Nom-Sup：4.6 ns
传播延迟（tpd）：5.3 ns认证状态：Not Qualified
筛选级别：MIL-PRF-38535座面最大高度：5.08 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：NO技术：BICMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
翻译：N/A宽度：7.62 mm
Base Number Matches：1

SNJ54LVTH2245J 数据手册

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SCBS707E − SEPTEMBER 1997 − REVISED OCTOBER 2003  
SN54LVTH2245 . . . J OR W PACKAGE  
SN74LVTH2245 . . . DB, DGV, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
)
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
DIR  
A1  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
V
CC  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
OLP  
CC  
= 3.3 V, T = 25°C  
A2  
A
A3  
B-Port Outputs Have Equivalent 22-Ω  
Series Resistors, So No External Resistors  
Are Required  
A4  
A5  
A6  
D
D
I
and Power-Up 3-State Support Hot  
off  
A7  
Insertion  
A8  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
GND  
SN54LVTH2245 . . . FK PACKAGE  
(TOP VIEW)  
D Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
3
2
1 20 19  
18  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
B1  
B2  
B3  
B4  
B5  
17  
16  
15  
14  
description/ordering information  
These octal bus transceivers are designed  
specifically for low-voltage (3.3-V) V  
operation,  
CC  
9 10 11 12 13  
but with the capability to provide a TTL interface  
to a 5-V system environment.  
These devices are designed for asynchronous  
communication between data buses. They  
transmit data from the A bus to the B bus or from  
the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)  
input can be used to disable the devices so the buses are effectively isolated.  
ORDERING INFORMATION  
ORDERABLE  
†
T
PACKAGE  
TOP-SIDE MARKING  
A
PART NUMBER  
SN74LVTH2245DW  
SN74LVTH2245DWR  
SN74LVTH2245NSR  
SN74LVTH2245DBR  
SN74LVTH2245PW  
SN74LVTH2245PWR  
SN74LVTH2245DGVR  
SNJ54LVTH2245J  
Tube  
SOIC − DW  
LVTH2245  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
LVTH2245  
LK245  
SSOP − DB  
−40°C to 85°C  
−55°C to 125°C  
TSSOP − PW  
LK245  
Tape and reel  
Tape and reel  
Tube  
TVSOP − DGV  
CDIP − J  
LK245  
SNJ54LVTH2245J  
SNJ54LVTH2245W  
SNJ54LVTH2245FK  
CFP − W  
Tube  
SNJ54LVTH2245W  
SNJ54LVTH2245FK  
LCCC − FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...17

中文翻译

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