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SNJ54LVTH245AWR PDF预览

SNJ54LVTH245AWR

更新时间: 2024-11-26 13:13:51
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
21页 943K
描述
LVT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, CDFP20, CERAMIC, DFP-20

SNJ54LVTH245AWR 技术参数

生命周期:Obsolete零件包装代码:DFP
包装说明:CERAMIC, DFP-20针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.33Is Samacsys:N
其他特性:WITH DIRECTION CONTROL系列:LVT
JESD-30 代码:R-GDFP-F20长度:13.09 mm
逻辑集成电路类型:BUS TRANSCEIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DFP封装形状:RECTANGULAR
封装形式:FLATPACK传播延迟(tpd):4.2 ns
认证状态:Not Qualified筛选级别:MIL-PRF-38535
座面最大高度:2.45 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:MILITARY端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
宽度:6.92 mmBase Number Matches:1

SNJ54LVTH245AWR 数据手册

 浏览型号SNJ54LVTH245AWR的Datasheet PDF文件第2页浏览型号SNJ54LVTH245AWR的Datasheet PDF文件第3页浏览型号SNJ54LVTH245AWR的Datasheet PDF文件第4页浏览型号SNJ54LVTH245AWR的Datasheet PDF文件第5页浏览型号SNJ54LVTH245AWR的Datasheet PDF文件第6页浏览型号SNJ54LVTH245AWR的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇꢈ ꢃ ꢂ ꢉꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢂꢉ  
ꢌ ꢍꢌ ꢎꢅ ꢉꢏꢆ ꢐ ꢑꢆꢉꢄ ꢏꢒꢀ ꢆ ꢓꢉꢁꢀ ꢑꢔ ꢕ ꢅꢔ ꢓ ꢀ  
ꢖ ꢕꢆ ꢇ ꢌ ꢎꢀꢆꢉꢆ ꢔ ꢐ ꢒꢆ ꢗꢒ ꢆꢀ  
SCBS130T − MAY 1992 − REVISED SEPTEMBER 2003  
D
D
D
D
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
D
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
)
CC  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
D
D
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
A
Support Unregulated Battery Operation  
Down to 2.7 V  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
I
and Power-Up 3-State Support Hot  
off  
Insertion  
SN74LVTH245A . . . RGY PACKAGE  
(TOP VIEW)  
SN54LVTH245A . . . FK PACKAGE  
(TOP VIEW)  
SN54LVTH245A . . . J OR W PACKAGE  
SN74LVTH245A . . . DB, DW, NS,  
OR PW PACKAGE  
(TOP VIEW)  
1
20  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DIR  
A1  
V
CC  
3
2
1 20 19  
18  
19  
18  
17  
16  
15  
14  
13  
12  
2
3
4
5
6
7
8
9
A3  
A4  
A5  
A6  
A7  
B1  
B2  
B3  
B4  
B5  
4
5
6
7
8
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
17  
16  
15  
14  
A2  
A3  
A4  
A5  
9 10 11 12 13  
A6  
A7  
A8  
10  
11  
GND  
description/ordering information  
These octal bus transceivers are designed specifically for low-voltage (3.3-V) V  
capability to provide a TTL interface to a 5-V system environment.  
operation, but with the  
CC  
ORDERING INFORMATION  
ORDERABLE  
T
A
PACKAGE  
TOP-SIDE MARKING  
PART NUMBER  
SN74LVTH245ARGYR  
SN74LVTH245ADW  
SN74LVTH245ADWR  
SN74LVTH245ANSR  
SN74LVTH245ADBR  
SN74LVTH245APW  
SN74LVTH245APWR  
SN74LVTH245AGQNR  
SN74LVTH245AZQNR  
SNJ54LVTH245AJ  
QFN − RGY  
SOIC − DW  
Tape and reel  
Tube  
LXH245A  
LVTH245A  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
LVTH245A  
LXH245A  
SSOP − DB  
−40°C to 85°C  
TSSOP − PW  
LXH245A  
LXH245A  
Tape and reel  
VFBGA − GQN  
Tape and reel  
VFBGA − ZQN (Pb-free)  
CDIP − J  
Tube  
Tube  
Tube  
SNJ54LVTH245AJ  
SNJ54LVTH245AW  
SNJ54LVTH245AFK  
−55°C to 125°C  
CFP − W  
SNJ54LVTH245AW  
SNJ54LVTH245AFK  
LCCC − FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢐ ꢚ ꢥ ꢝ ꢜꢨ ꢣꢢ ꢠꢡ ꢢꢜ ꢞꢥ ꢧꢙ ꢟꢚ ꢠ ꢠꢜ ꢮꢕ ꢄꢎ ꢗꢓ ꢯ ꢎꢌꢰꢂ ꢌꢂꢊ ꢟꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢟ ꢝ ꢤ ꢠꢤ ꢡꢠꢤ ꢨ  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢭ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢍ  
ꢣ ꢚꢧ ꢤꢡꢡ ꢜ ꢠꢩꢤ ꢝ ꢫꢙ ꢡꢤ ꢚ ꢜꢠꢤ ꢨꢍ ꢐ ꢚ ꢟꢧ ꢧ ꢜ ꢠꢩꢤ ꢝ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢡ ꢊ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢙꢜ ꢚ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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