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SNJ54LVTH273J PDF预览

SNJ54LVTH273J

更新时间： 2024-11-03 23:03:19
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
13页 313K
描述
3.3-V ABT OCTAL D-TYPE FLIP-FLOPS WITH CLEAR

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SNJ54LVTH273J 数据手册

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ꢘ ꢗꢆ ꢇ ꢑ ꢄꢕ ꢎꢙ  
SCBS136M − MAY 1992 − REVISED OCTOBER 2003  
D
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
D
D
I
Supports Partial-Power-Down-Mode  
off  
Operation  
3.3-V V  
)
CC  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
D
D
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
= 3.3 V, T = 25°C  
A
OLP  
CC  
Support Unregulated Battery Operation  
Down To 2.7 V  
D
D
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
D
Buffered Clock and Direct-Clear Inputs  
Individual Data Input to Each Flip-Flop  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
D
SN54LVTH273 . . . J PACKAGE  
SN74LVTH273 . . . DB, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
SN54LVTH273 . . . FK PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
CLR  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
CLK  
3
2
1
20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
17 7D  
4
5
6
7
8
16  
15  
14  
7Q  
6Q  
6D  
9 10 11 12 13  
GND  
description/ordering information  
These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) V  
capability to provide a TTL interface to a 5-V system environment.  
operation, but with the  
CC  
The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D)  
inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going  
edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the  
transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the  
D-input signal has no effect at the output.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
Tube  
SN74LVTH273DW  
SN74LVTH273DWR  
SN74LVTH273NSR  
SN74LVTH273DBR  
SN74LVTH273PW  
SN74LVTH273PWR  
SNJ54LVTH273J  
SOIC − DW  
LVTH273  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
LVTH273  
LXH273  
−40°C to 85°C  
−55°C to 125°C  
SSOP − DB  
TSSOP − PW  
LXH273  
Tape and reel  
Tube  
CDIP − J  
SNJ54LVTH273J  
LCCC − FK  
Tube  
SNJ54LVTH273FK  
SNJ54LVTH273FK  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢚ ꢁ ꢄꢕꢀꢀ ꢐ ꢆꢇ ꢕꢙꢘ ꢗꢀ ꢕ ꢁ ꢐꢆꢕꢒ ꢛꢜ ꢝꢞ ꢟꢠꢡ ꢢꢣꢤ ꢥꢛ ꢡꢠ ꢥꢛꢦ ꢝꢥꢞ ꢔꢙ ꢐ ꢒ ꢚ ꢑꢆ ꢗꢐ ꢁ  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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