Datasheet > SNJ54LVTT240DW

SNJ54LVTT240DW

更新时间： 2024-11-05 09:19:03

品牌	Logo	应用领域
德州仪器 - TI		驱动光电二极管输出元件
页数	文件大小	规格书
6页	106K
描述
LVT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, PLASTIC, SO-20

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SNJ54LVTT240DW 数据手册

SN54LVTT240, SN74LVTT240

3.3-V ABT OCTAL BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCES005 – FEBRUARY 1995

SN54LVTT240 . . . J OR W PACKAGE

SN74LVTT240 . . . DB, DW, OR PW PACKAGE

(TOP VIEW)

• State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V

Operation and Low-Static Power

Dissipation

1OE

1A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1

GND

• Supports Mixed-Mode Signal Operation

2OE

1Y1

2A4

1Y2

2A3

1Y3

(5-V Input and Output Voltages With

3.3-V V

)

• Supports Unregulated Battery Operation

Down to 2.7 V

• Typical V

(Output Ground Bounce)

OLP

< 0.8 V at V

= 3.3 V, T = 25°C

13 2A2

12 1Y4

• Latch-Up Performance Exceeds 500 mA

2A1

Per JEDEC Standard JESD-17

• Supports Live Insertion

SN54LVTT240 . . . FK PACKAGE

(TOP VIEW)

• Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), Thin Shrink Small-Outline (PW)

Packages, Ceramic Chip Carriers (FK),

Ceramic Flat (W) Packages, and Ceramic

(J) DIPs

20 19

1Y1

2A4

1Y2

2A3

1Y3

1A2

2Y3

1A3

2Y2

1A4

description

These octal buffers and line drivers are designed

specifically for low-voltage (3.3-V) V operation,

9 10 11 12 13

but with the capability to provide a TTL interface to

a 5-V system environment.

The ’LVTT240 is organized as two 4-bit buffer/line

drivers with separate output-enable (OE) inputs.

When OE is low, the device passes data from the

A inputs to the Y outputs. When OE is high, the

outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74LVTT240 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count

and functionality of standard small-outline packages in less than half the printed-circuit-board area.

The SN54LVTT240 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74LVTT240 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each buffer)

INPUTS

OUTPUT

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6

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与SNJ54LVTT240DW相关器件

型号	品牌	获取价格	描述	数据表
SNJ54LVTT240DWR	TI	获取价格	LVT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, PLASTIC, SO-20
SNJ54LVTT240J	TI	获取价格	LVT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, CDIP20, CERAMIC, DIP-20
SNJ54LVTT240W	TI	获取价格	LVT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, CDFP20, CERAMIC, DFP-20
SNJ54LVTT244W	TI	获取价格	LVT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDFP20, CERAMIC, DFP-20
SNJ54LVU04AFK	TI	获取价格	HEX INVERTERS
SNJ54LVU04AJ	TI	获取价格	HEX INVERTERS
SNJ54LVU04AW	TI	获取价格	HEX INVERTERS
SNJ54S00FK	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SNJ54S00J	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SNJ54S00J-00	TI	获取价格	S SERIES, QUAD 2-INPUT NAND GATE, CDIP14

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