5秒后页面跳转
捷配首页

Datasheet > SNJ54LVTH18502AHV
SNJ54LVTH18502AHV PDF预览

SNJ54LVTH18502AHV

更新时间： 2024-01-25 01:58:16
品牌 Logo 应用领域
德州仪器 - TI 总线收发器测试
页数 文件大小 规格书
38页 610K
描述
3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

阅读下载

中文翻译

获取价格

SNJ54LVTH18502AHV 技术参数

生命周期：Active零件包装代码：QFP
包装说明：QFF, QFL68,.5SQ,25针数：68
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.46其他特性：SUPPORTS IEEE STANDARD 1149.1-1990 BOUNDARY SCAN
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：LVTJESD-30 代码：S-GQFP-F68
长度：12.51 mm负载电容（CL）：50 pF
逻辑集成电路类型：BOUNDARY SCAN REG BUS TRANSCEIVER最大I（ol）：0.064 A
位数：9功能数量：2
端口数量：2端子数量：68
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：QFF
封装等效代码：QFL68,.5SQ,25封装形状：SQUARE
封装形式：FLATPACK包装方法：TUBE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
最大电源电流（ICC）：24 mAProp。Delay @ Nom-Sup：4.9 ns
传播延迟（tpd）：8.1 ns认证状态：Not Qualified
筛选级别：MIL-PRF-38535座面最大高度：3.86 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：MILITARY端子形式：FLAT
端子节距：0.635 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：12.51 mm
Base Number Matches：1

SNJ54LVTH18502AHV 数据手册

 浏览型号SNJ54LVTH18502AHV的Datasheet PDF文件第2页浏览型号SNJ54LVTH18502AHV的Datasheet PDF文件第3页浏览型号SNJ54LVTH18502AHV的Datasheet PDF文件第4页浏览型号SNJ54LVTH18502AHV的Datasheet PDF文件第5页浏览型号SNJ54LVTH18502AHV的Datasheet PDF文件第6页浏览型号SNJ54LVTH18502AHV的Datasheet PDF文件第7页 
ꢀ
ꢁ
ꢂ
ꢃ
ꢄꢅ  
ꢆ
ꢇ
ꢈ
ꢉ
ꢂ
ꢊ
ꢋ
ꢌ
ꢍ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢋ
ꢂ
ꢊ
ꢋ
ꢌ
ꢍ
ꢀ
ꢁ
ꢎ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢂ
ꢏ ꢐꢏ ꢑꢅ ꢌꢒꢆ ꢀꢓ ꢌꢁ ꢆ ꢔꢀꢆ ꢕ ꢔꢅ ꢖ ꢓꢔ ꢀ  
ꢊ
ꢋ
ꢌ
ꢍ
ꢀ
ꢁ
ꢎ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢋ
ꢂ
ꢊ
ꢋ
ꢌ
ꢗ
ꢖ
ꢆ
ꢇ
ꢈ
ꢉ
ꢑ
ꢒ
ꢖ
ꢆ
ꢘ
ꢁ
ꢖ
ꢅ
ꢔ
ꢙ
ꢀ
ꢌ
ꢄ
ꢒ
ꢘ
ꢀ
ꢆ
ꢙ
ꢌ
ꢁ
ꢀ
ꢓ
ꢔ
ꢖ
ꢅ
ꢔ
ꢙ
ꢀ
SCBS668C − JULY 1996 − REVISED JUNE 2004  
D
D
D
Members of the Texas Instruments  
SCOPE Family of Testability Products  
Members of the Texas Instruments  
WidebusFamily  
State-of-the-Art 3.3-V ABT Design Supports  
Mixed-Mode Signal Operation (5-V Input  
D
Compatible With the IEEE Standard  
1149.1-1990 (JTAG) Test Access Port and  
Boundary-Scan Architecture  
D
SCOPE Instruction Set  
− IEEE Standard 1149.1-1990 Required  
Instructions and Optional CLAMP and  
HIGHZ  
and Output Voltages With 3.3-V V  
)
CC  
− Parallel-Signature Analysis at Inputs  
− Pseudorandom Pattern Generation From  
Outputs  
− Sample Inputs/Toggle Outputs  
− Binary Count From Outputs  
− Device Identification  
D
D
Support Unregulated Battery Operation  
Down to 2.7 V  
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
− Even-Parity Opcodes  
D
D
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup Resistors  
D
Packaged in 64-Pin Plastic Thin Quad Flat  
(PM) Packages Using 0.5-mm  
Center-to-Center Spacings and 68-Pin  
Ceramic Quad Flat (HV) Packages Using  
25-mil Center-to-Center Spacings  
B-Port Outputs of ’LVTH182502A Devices  
Have Equivalent 25-Ω Series Resistors, So  
No External Resistors Are Required  
description  
The ’LVTH18502A and ’LVTH182502A scan test devices with 18-bit universal bus transceivers are members  
of the Texas Instruments SCOPEtestability integrated-circuit family. This family of devices supports IEEE  
Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to  
the test circuitry is accomplished via the 4-wire test access port (TAP) interface.  
Additionally, these devices are designed specifically for low-voltage (3.3-V) V  
capability to provide a TTL interface to a 5-V system environment.  
operation, but with the  
CC  
In the normal mode, these devices are 18-bit universal bus transceivers, that combine with D-type latches and  
D-type flip-flops, they allow data to flow in the transparent, latched, or clocked modes. Another use is as two  
9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot  
samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating  
the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.  
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),  
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when  
LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level.  
Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the  
B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is  
similar to A-to-B data flow, but uses the OEBA, LEBA, and CLKBA inputs.  
In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test circuitry  
is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs  
boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SCOPE, Widebus, and UBT are trademarks of Texas Instruments.  
Copyright 2004, Texas Instruments Incorporated  
ꢘ ꢁ ꢄꢔꢀꢀ ꢚ ꢆꢇ ꢔꢙꢗ ꢖꢀ ꢔ ꢁ ꢚꢆꢔꢕ ꢛꢜ ꢝꢞ ꢟꢠꢡ ꢢꢣꢤ ꢥꢛ ꢡꢠ ꢥꢛꢦ ꢝꢥꢞ ꢧꢙ ꢚ ꢕ ꢘ ꢓꢆ ꢖꢚ ꢁ  
ꢛ
ꢕ
ꢌ
ꢆ
ꢌ
ꢝ
ꢥ
ꢨ
ꢠ
ꢩ
ꢣ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢡ
ꢢ
ꢩ
ꢩ
ꢤ
ꢥ
ꢛ
ꢦ
ꢞ
ꢠ
ꢨ
ꢪ
ꢢ
ꢫ
ꢬ
ꢝ
ꢡ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢟ
ꢦ
ꢤ
ꢐ
ꢧ
ꢩ
ꢠ
ꢟ
ꢢ
ꢡ
ꢛ
ꢞ
ꢡ
ꢠ
ꢥ
ꢨ
ꢠ
ꢩ
ꢣ
ꢛ
ꢠ
ꢞ
ꢪ
ꢤ
ꢡ
ꢝ
ꢨ
ꢝ
ꢡ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢞ
ꢪ
ꢤ
ꢩ
ꢛ
ꢜ
ꢤ
ꢛ
ꢤ
ꢩ
ꢣ
ꢞ
ꢠ
ꢨ
ꢆ
ꢤ
ꢭ
ꢦ
ꢞ
ꢖ
ꢥ
ꢞ
ꢛ
ꢩ
ꢢ
ꢣ
ꢤ
ꢥ
ꢛ
ꢞ
ꢞ
ꢛ
ꢦ
ꢥ
ꢟ
ꢦ
ꢩ
ꢟ
ꢮ
ꢦ
ꢩ
ꢩ
ꢦ
ꢥ
ꢛ
ꢯ
ꢐ
ꢧ
ꢩ
ꢠ
ꢟ
ꢢ
ꢡ
ꢛ
ꢝ
ꢠ
ꢥ
ꢪꢦ ꢩ ꢦ ꢣ ꢤ ꢛ ꢤ ꢩ ꢞ ꢐ  
ꢪ
ꢩ
ꢠ
ꢡ
ꢤ
ꢞ
ꢞ
ꢝ
ꢥ
ꢰ
ꢟ
ꢠ
ꢤ
ꢞ
ꢥ
ꢠ
ꢛ
ꢥ
ꢤ
ꢡ
ꢤ
ꢞ
ꢞ
ꢦ
ꢩ
ꢝ
ꢬ
ꢯ
ꢝ
ꢥ
ꢡ
ꢬ
ꢢ
ꢟ
ꢤ
ꢛ
ꢤ
ꢞ
ꢛ
ꢝ
ꢥ
ꢰ
ꢠ
ꢨ
ꢦ
ꢬ
ꢬ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...38

中文翻译

下载PDF

与SNJ54LVTH18502AHV相关器件

型号 品牌 获取价格 描述 数据表
SNJ54LVTH18514HKC TI

获取价格

 		LVT SERIES, 20-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CDFP64, CERAMIC, DFP-64
SNJ54LVTH18640WD TI

获取价格

 		LVT SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, INVERTED OUTPUT, CDFP56
SNJ54LVTH2245FK TI

获取价格

 		3.3-V ABT OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SNJ54LVTH2245J TI

获取价格

 		3.3-V ABT OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SNJ54LVTH2245W TI

获取价格

 		3.3-V ABT OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SNJ54LVTH240FK TI

获取价格

 		3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SNJ54LVTH240J TI

获取价格

 		3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SNJ54LVTH240W TI

获取价格

 		3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SNJ54LVTH241FK TI

获取价格

 		3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SNJ54LVTH241J TI

获取价格

 		3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

与SNJ54LVTH18502AHV相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证