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SN74LVC573ARGYR

更新时间： 2024-11-26 09:12:47
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德州仪器 - TI 锁存器输出元件
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28页 1057K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN74LVC573ARGYR 数据手册

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SN54LVC573A, SN74LVC573A  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS300R–JANUARY 1993–REVISED SEPTEMBER 2005  
FEATURES  
•
•
•
•
Operate From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 6.9 ns at 3.3 V  
•
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Typical VOLP (Output Ground Bounce) <0.8 V  
at VCC = 3.3 V, TA = 25°C  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
•
•
Typical VOHV (Output VOH Undershoot) >2 V at  
VCC = 3.3 V, TA = 25°C  
Support Mixed-Mode Signal Operation on All  
Ports (5-V Input/Output Voltage With 3.3-V  
– 1000-V Charged-Device Model (C101)  
xxxxx  
VCC  
)
SN54LVC573A . . . J OR W PACKAGE  
SN74LVC573A . . . DB, DGV, DW, N,  
NS, OR PW PACKAGE  
SN74LVC573A . . . RGY PACKAGE  
(TOP VIEW)  
SN54LVC573A . . . FK PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
1
20  
OE  
1D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
3
9
2
1 20 19  
18  
2Q  
3Q  
4Q  
5Q  
3D  
4D  
5D  
6D  
7D  
2
3
4
5
6
7
8
9
19  
18  
17  
16  
15  
14  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
4
5
6
7
8
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
LE  
17  
16  
15  
2D  
3D  
4D  
5D  
14 6Q  
10 11 12 13  
6D  
13 7Q  
12  
7D  
8D  
GND  
8Q  
10  
11  
DESCRIPTION/ORDERING INFORMATION  
The SN54LVC573A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation, and the  
SN74LVC573A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.  
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. They are particularly suitable for implementing buffer registers, input/output (I/O) ports,  
bidirectional bus drivers, and working registers.  
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q  
outputs are latched at the logic levels at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the  
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines  
without interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the  
outputs, preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1993–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
On products compliant to MIL-PRF-38535, all parameters are  
Instruments standard warranty. Production processing does not  
tested unless otherwise noted. On all other products, production  
necessarily include testing of all parameters.  
processing does not necessarily include testing of all parameters.  
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SN74LVC573ARGYR 替代型号

型号 品牌 替代类型 描述 数据表
74LVC573ABQ NEXPERIA

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